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參數(shù)資料
| 型號： | TDA5147K |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 運動控制電子 |
| 英文描述： | 12 V Voice Coil Motor VCM driver and spindle motor drive combination chip |
| 中文描述： | VOICE COIL MOTOR CONTROLLER, PQCC52 |
| 文件頁數(shù)： | 9/32頁 |
| 文件大?。?/td> | 154K |
| 代理商： | TDA5147K |
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1996 Jul 26
9
Philips Semiconductors
Product specification
12 V Voice Coil Motor (VCM) driver and
spindle motor drive combination chip
TDA5147K
The duty factor is arranged so that at 100%, the voltage SPWMFLT = 1.74 V and at a 5% duty factor SPWMFLT = 0 V.
This is to ensure that at 0% duty factor the current will be zero (allowances for circuit tolerances).
The input decoder is driven by three lines which define the windings to be energized. The input decoder must then
translate these lines to six lines to drive the six output drivers. The truth table is given in Table 1.
Table 1
Input decoder truth table
Note
1.
X = 3-state.
CONDITION
SCNTL1
SCNTL2
SCNTL3
SDRVU
(1)
SDRVV
(1)
SDRVW
(1)
Disable
Dynamic brake
State 1
State 2
State 3
State 4
State 5
State 6
Under voltage
LOW
HIGH
HIGH
HIGH
HIGH
LOW
LOW
LOW
LOW
HIGH
HIGH
LOW
LOW
LOW
HIGH
HIGH
LOW
HIGH
LOW
LOW
HIGH
HIGH
HIGH
LOW
X
X
X
HIGH
LOW
X
HIGH
HIGH
X
LOW
X
HIGH
X
LOW
LOW
X
HIGH
HIGH
X
HIGH
HIGH
HIGH
X
LOW
LOW
X
X
VCM driver
The VCM driver is a linear, class AB, H-bridge type power
driver with all power devices internal to the chip. In addition
to the power stage a sense resistor enables VCM current
to be measured and brought out to a separate ADC via the
V
ISENS2
pin. The reference voltage for the V
ISENS2
output
is provided externally. The current level to the VCM is
controlled via two PWM signals that are generated by the
digital circuit. The input voltage at pin 47 (V
IPWMH
)
represents a weighting of 32 times more than the input
voltage at pin 46 (V
IPWML
), thus the current command is
equal to 32
×
duty factor (V
IPWML
+ V
IPWMH
). These PWM
signals are filtered by an internal 3rd-order low-pass filter
(Butterworth filter). The bandwidth of this low-pass filter is
nominally 40 kHz (less than 2 degrees lag at 500 Hz), but
the real pole may be adjustable by an external capacitor.
The analog output of the filter depends on the duty factor
of the PWM signal and not on the logic level.
Fig.5 Block diagram of the PWM filter.
handbook, full pagewidth
LEVEL
CONVERTOR
Vref
PWM (MSD)
SUM
LEVEL
CONVERTOR
PWM (LSB)
32 : 1
ATTENUATION
UNITY
GAIN
LOW-PASS
analog
output
MBH019
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