參數(shù)資料
型號(hào)： TDA5147K
廠商： NXP SEMICONDUCTORS
元件分類： 運(yùn)動(dòng)控制電子
英文描述： 12 V Voice Coil Motor VCM driver and spindle motor drive combination chip
中文描述： VOICE COIL MOTOR CONTROLLER, PQCC52
文件頁數(shù)： 10/32頁
文件大?。?/td> 154K
代理商： TDA5147K
1996 Jul 26
10
Philips Semiconductors
Product specification
12 V Voice Coil Motor (VCM) driver and
spindle motor drive combination chip
TDA5147K
PARK
ENABLE
A 3-state-level mode line (V
PCNTL
) has been included that
will:
1.
Enable VCM drivers; V
CCA1
(normal).
2.
Disable VCM drivers; 0.5V
CCA1
.
3.
PARK (soft retract the actuator); 0 V.
Enable VCM drivers
When the enable signal is HIGH, the VCM drivers are
controlled by the two PWM inputs. The two digital signals
convert the duty factor to a voltage level at V
FLTOUT
. At a
100% duty factor the V
FLTINP
voltage is approximately 1 V
above V
ref(o)
. At a 0% duty factor the V
FLTINP
voltage is
approximately
1 V below V
ref(o)
. At a 50% duty factor, the
voltage level is equal to V
ref(o)
(typical 4 V). The V
FLTINP
voltage is amplified, filtered and output at V
FLTOUT
. The
voltage at V
FLTOUT
varies between
±
2 V about V
ref(o)
. The
V
FLTOUT
voltage, in conjunction with the sense resistor
amplifier, drives the two VCM drivers as illustrated in Fig.8.
The transconductance equation that governs the voltage
from V
FLTINP
to I
coil
is:
I
V
FLTINP
V
ref o
–
Amps per Volt
In a typical application:
I
V
FLTINP
V
ref o
–
The transconductance is variable by selecting external
resistors R2/R1 and sense resistors R
s
Disable VCM drivers
With the PARK enable signal at 0.5V the VCM drivers are
disabled while the rest of the circuits remain enabled.
A sleep mode is initiated when the spindle and VCM are
disabled (this places the TDA5147K in its lowest power
setting).
G
m
---------------------------------------------
I
V
FLTOUT
V
ref o
–
(
)
-----------------------------------------------------
=
=
2
gain
----1
R1
R2
R
s
1
×
×
×
=
---------------------------------------------
2
4
10 k
6.6 k
×
0.33
----1
×
1 Amp per Volt
=
=
A
CTUATOR PARK
Retracting the actuator can be accomplished by driving
V
PCNTL
LOW in conjunction with either the spindle is
turning or a brake voltage has been applied. An adjustable
retract voltage of 1.2 V (max.) is applied between the V
CMN
and V
CMP
outputs. The retract circuit obtains its retract
current from the spindle SDRVU phase. If the SDRVU
phase is zero there will be no retract voltage.
The retract voltage is determined by two external resistors.
One end is tied to V
CMN
and the other to ground. The
common point is tied to pin 22 (RET
ADJ
); see Fig.1 for
additional information.
The calculation of V
RETRACT
is as follows:
Where 0.65 is V
BE
at 25
°
C
V
BE
/
T =
2 mV/
°
C; 50 k
can vary by
±
30%
It should be noted that R2 has to be less than 10 k
.
Power-on reset
The power-on reset circuit monitors the voltage levels of
both the +5 V and the +12 V supply voltages as shown
in Fig.6. The POR (active LOW) logic line is set HIGH
following a supply voltage rise above a specified voltage
threshold plus a hysteresis, and delayed by a time, t
C
that
is controlled by an external capacitor. This POR signal
should remain HIGH until either the +5 or +12 V supplies
drop below the voltage threshold, at which point the POR
line should be asserted LOW.
The t
C
timing is set by the following equation:
C
V
th
I
Where V
th
= 2.5 V and I is 12
μ
A (typ.).
A negative going pulse width of 5
μ
s on either the
+5 or +12 V rail will provide a full output pulse. If another
trigger pulse occurs before the output is completed a new
output pulse will be originated. This implies the power-on
reset circuit is a retriggerable one-shot with a maximum
trigger pulse of 5
μ
s (see Fig.7).
V
RETRACT
0.65
1
R2
+
R1
50 k
+
×
=
t
C
------------------
=
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