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參數(shù)資料
| 型號： | TDA10021HT |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費家電 |
| 英文描述： | DVB-C channel receiver |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP64 |
| 封裝： | 10 X 10 MM, 1 MM HEIGHT, PLASTIC, MS-026, SOT-357-1, TQFP-64 |
| 文件頁數(shù)： | 6/16頁 |
| 文件大小： | 92K |
| 代理商： | TDA10021HT |
2001 Oct 01
6
Philips Semiconductors
Product specification
DVB-C channel receiver
TDA10021HT
Note
1.
All inputs (I) are TTL, 5 V tolerant (except pins XIN, V
IP
and V
IM
). OD are open-drain outputs, so they must be
connected by a pull-up resistor to either V
DDD33
or V
DDD50
.
DO[7:4]
37 to 40
O
data output bus: this 8-bit parallel data is the output from the TDA10021HT after
demodulation, de-interleaving, RS decoding and de-scrambling. When one of the
two possible parallel interfaces is selected (parameter SERINT = 0, index 20) then
DO[7:0] is the transport stream output. When the serial interface is selected
(parameter SERINT = 1, index 20) then the serial output is on pin DO[0].
digital supply voltage for the core (1.8 V typ.)
digital ground for the core
digital supply voltage for the pads (3.3 V typ.)
digital ground for the pads
data output bus: this 8-bit parallel data is the output from the TDA10021HT after
demodulation, de-interleaving, RS decoding and de-scrambling. When one of the
two possible parallel interfaces is selected then DO[7:0] is the transport stream
output. When the serial interface is selected then the serial output is on pin DO[0].
ground return for the digital switching circuitry (ADC)
power supply input for the digital switching circuitry 1.8 V (ADC)
ground return for the analog clock drivers (ADC)
power supply input for the analog clock drivers 3.3 V (ADC)
this is a positive voltage reference for the ADC. It is derived from the internal band
gap voltage, VBG, with an on-chip fully differential amplifier.
this is the negative voltage reference for the ADC. It is derived from the internal
band gap voltage, VBG, with an on-chip fully differential amplifier.
power supply input for the analog circuits 3.3 V (ADC)
ground return for analog circuits (ADC)
negative input to the ADC: this pin is DC biased to half-supply through an internal
resistor divider (2
×
20 k
resistors). In order to stay in the range of the ADC,
V
IP
V
IM
should remain between the input range corresponding to the SW
register (index 1B
default value = 0.5 V).
positive input to the ADC: this pin is DC biased to half-supply through an internal
resistor divider (2
×
20 k
resistors). In order to stay in the range of the ADC,
V
IP
V
IM
should remain between the input range corresponding to the SW
register (index 1B
default value = 0.5 V).
ground return for analog circuits (ADC)
power supply input for the analog circuits 3.3 V (ADC)
power supply for the PLL digital section 1.8 V
ground connection for the PLL digital section
ground connection for the PLL analog section
power supply for the PLL analog section 3.3 V
V
DDDI8
V
SSD18
V
DDD33
V
SSD33
DO[3:0]
41
42
43
44
S
G
S
G
O
45 to 48
V
SSD1
V
DDD1
V
SSA2
V
DDA2
V
ref(pos)
49
50
51
52
53
G
S
G
S
O
V
ref(neg)
54
O
V
DDA3
V
SSA3
V
IM
55
56
57
S
G
I
V
IP
58
I
V
SSA3
V
DDA3
V
CCD(PLL)
DGND
PLLGND
V
CCA(PLL)
59
60
61
62
63
64
G
S
S
G
G
S
SYMBOL
PIN
TYPE
(1)
DESCRIPTION
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