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參數(shù)資料
| 型號(hào)： | TDA10021HT |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | DVB-C channel receiver |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP64 |
| 封裝： | 10 X 10 MM, 1 MM HEIGHT, PLASTIC, MS-026, SOT-357-1, TQFP-64 |
| 文件頁(yè)數(shù)： | 4/16頁(yè) |
| 文件大?。?/td> | 92K |
| 代理商： | TDA10021HT |
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2001 Oct 01
4
Philips Semiconductors
Product specification
DVB-C channel receiver
TDA10021HT
PINNING
SYMBOL
PIN
TYPE
(1)
DESCRIPTION
V
DDD18
XIN
1
2
S
I
digital supply voltage for the core (1.8 V typ.)
XTAL oscillator input pin: a fundamental XTAL oscillator is connected between the
XIN and XOUT pins. The XTAL frequency must be chosen so that the system
frequency SYSCLK (XIN
×
multiplying factor of the PLL) equals 1.6 times the tuner
output intermediate frequency; i.e. SYSCLK = 1.6
×
IF.
XTAL oscillator output pin: a fundamental XTAL oscillator is connected between the
XIN and XOUT pins
digital ground for the core
sampling clock: this output clock can be fed to an external 10-bit ADC as the
sampling clock; SACLK = SYSCLK/2
test input pin: in normal mode, pin TEST must be connected to ground
digital supply voltage for the core (1.8 V typ.)
digital ground for the core
first PWM encoded output signal for AGC tuner: this signal is fed to the AGC
amplifier through a single RC network. The maximum signal frequency on the
VAGC output is XIN/16. AGC information is refreshed every 1024 symbols.
IICDIV: this pin allows the frequency of the I
2
C-bus internal system clock to be
selected, depending on the crystal frequency. The internal I
2
C-bus clock is a
division of XIN by 4
IICDIV
.
second PWM encoded output signal for the AGC IF: This signal is fed to the AGC
amplifier through a single RC network. The maximum signal frequency on the
VAGC output is XIN/16. AGC information is refreshed every 1024 symbols.
However AGCIF can also be configured to output a PWM signal, the value of which
can be programmed through the I
2
C-bus interface.
SADDR is the LSB of the I
2
C-bus address of the TDA10021HT. The MSBs are
internally set to 000110. Therefore the complete I
2
C-bus address of the
TDA10021HT is (MSB to LSB) 0, 0, 0, 1, 1, 0 and SADDR.
digital supply voltage for the pad 5.0 V (necessary for 5 V tolerant inputs)
digital supply voltage for the pads (3.3 V typ.)
digital ground for the pads
the CLR# input is asynchronous and active LOW, and clears the TDA10021HT:
When CLR# goes LOW, the circuit immediately enters its reset mode and normal
operation will resume 4 XIN falling edges after CLR# returns HIGH. The I
2
C-bus
register contents are all initialized to their default values. The minimum width of
CLR# at LOW level is 4 XIN clock periods.
I
2
C-bus clock input: SCL should nominally be a square wave with a maximum
frequency of 400 kHz. SCL is generated by the system I
2
C-bus master.
SDA is a bidirectional signal: it is the serial input/output of the I
2
C-bus internal block.
A pull-up resistor (typically 4.7 k
) must be connected between SDA and V
DDD50
for
proper operation (open-drain output).
SDAT is equivalent to SDA I/O of the TDA10021HT but can be 3-stated by I
2
C-bus
programming. It is actually the output of a switch controlled by parameter BYPIIC of
register TEST (index 0F). SDAT is an open-drain output and therefore requires an
external pull-up resistor.
XOUT
3
O
V
SSD18
SACLK
4
5
G
O
TEST
V
DDD18
V
SSD18
AGCTUN
6
7
8
9
I
S
G
O/OD
IICDIV
10
I
AGCIF
11
O/OD
SADDR
12
I
V
DDD50
V
DDD33
V
SSD33
CLR#
13
14
15
16
S
S
G
I
SCL
17
I
SDA
18
I/OD
SDAT
19
I/OD
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