參數(shù)資料
型號： TCS59SM808BFTL-75
廠商： Toshiba Corporation
英文描述： 8M×4Banks×8Bits Synchronous DRAM(4組8M×8位同步動態(tài)RAM)
中文描述： 8米× 4Banks × 8位同步DRAM（4組8米× 8位同步動態(tài)RAM）的
文件頁數(shù)： 38/49頁
文件大?。?/td> 2423K
代理商： TCS59SM808BFTL-75
TC59SM816/08/04BFT/BFTL-70,-75,-80
2000-03-14 38/49
Addressing sequence of Sequential mode
A column access is performed by incrementing the column address input to the device. The address is
varied by the Burst Length as shown in Table 2.
Table 2. Addressing sequence for Sequential mode
DATA
Access Address
Burst Length
Data0
n
Data1
n
+
1
Data2
n
+
2
Data3
n
+
3
Data4
n
+
4
Data5
n
+
5
Data6
n
+
6
Data7
n
+
7
2 words (Address bits is A0)
not carried from A0
to A1
4 words (Address bits is A1, A0)
not carried from A1
to A2
8 words (Address bits is A2, A1, A0)
not carried from A2
to A3
Addressing sequence of Interleave mode
A column access is started from the input column address and is performed by inverting the address bits
in the sequence shown in Table 3.
Table 3. Addressing sequence for Interleave mode
DATA
Access Address
Burst Length
Data0
A8
A7
A6
A5
A4
A3
A2
A1
A0
Data1
A8
A7
A6
A5
A4
A3
A2
A1
0
A
Data2
A8
A7
A6
A5
A4
A3
A2
1
A
A0
Data3
A8
A7
A6
A5
A4
A3
A2
1
A
0
A
Data4
A8
A7
A6
A5
A4
A3
2
A
A1
A0
Data5
A8
A7
A6
A5
A4
A3
2
A
A1
0
A
Data6
A8
A7
A6
A5
A4
A3
2
A
1
A
A0
Data7
A8
A7
A6
A5
A4
A3
2
A
1
A
0
A
2
words
4 words
8 words
相關(guān)PDF資料
PDF描述
TCS59SM808BFTL-80 8M×4Banks×8Bits Synchronous DRAM(4組8M×8位同步動態(tài)RAM)
TCS59SM816BFT-70 4M×4Banks×16Bits Synchronous DRAM(4組4M×16位同步動態(tài)RAM)
TCS59SM816BFT-75 4M×4Banks×16Bits Synchronous DRAM(4組4M×16位同步動態(tài)RAM)
TCS59SM816BFT-80 4M×4Banks×16Bits Synchronous DRAM(4組4M×16位同步動態(tài)RAM)
TCS59SM816BFTL-70 4M×4Banks×16Bits Synchronous DRAM(4組4M×16位同步動態(tài)RAM)
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