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參數(shù)資料
| 型號： | TCM320AC54N |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | Codec |
| 英文描述： | MONOLITHIC SERIAL INTERFACE COMBINED PCM CODEC AND FILTER |
| 中文描述： | 整體式串行接口的PCM編解碼器和過濾器 |
| 文件頁數(shù)： | 4/23頁 |
| 文件大小： | 317K |
| 代理商： | TCM320AC54N |
TCM320AC36, TCM320AC37
VOICE-BAND AUDIO PROCESSORS (VBAP
)
SLWS003C – MAY 1992 – REVISED APRIL – 1998
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Terminal Functions
TERMINAL
NAME
NO.
I/O
DESCRIPTION
DW, N
—
PT
34
AGND
Ground return for all internal analog circuits
AVCC
CLK
—
4
5-V supply voltage for all internal analog circuits
11
19
I
Clock input. In the fixed-data-rate mode, CLK is the master clock input as well as the transmit and
receive data clock input . In the variable-data-rate mode, CLK is the master clock input only (digital).
DCLKR
7
14
I
Selection of fixed- or variable-data-rate operation. When DCLKR is connected to VCC, the device
operates in the fixed-data-rate mode. When DCLKR is not connected to VCC, the device operates in
the variable-data-rate mode, and DCLKR becomes the receive data clock (digital).
DGND
—
27
Ground return for all internal digital circuits
DIN
8
15
I
Receive data input. Input data is clocked in on consecutive negative transitions of the receive data
clock, which is CLK for a fixed data rate and DCLKR for a variable data rate (digital).
DOUT
13
21
O
Transmit data output. Transmit data is clocked out on consecutive positive transitions of the transmit
data clock, which is CLK for a fixed data rate and DCLKX for a variable data rate (digital).
DVCC
EARA
—
9
5-V supply voltage for all internal digital circuits
2
44
O
Earphone output. EARA forms a differential drive when used with the EARB signal (analog).
EARB
3
45
O
Earphone output. EARB forms a differential drive when used with the EARA signal (analog).
EARGS
4
46
I
Earphone gain set input of feedback signal for the earphone output. The ratio of an external potential
divider network connected across EARA and EARB adjusts the power amplifier gain. Maximum gain
occurs when EARGS is connected to EARB. Minimum gain occurs when EARGS is connected to
EARA. Earphone frequency response correction is performed using an RC approach (analog).
EARMUTE
10
17
I
Earphone output mute control signal. When EARMUTE is low, the output amplifier is disabled and no
audio is sent to the earphone (digital).
FSR
9
16
I
Frame-synchronization clock input for the receive channel. In the variable-data-rate mode, this signal
must remain high for the duration of the time slot. The receive channel enters the standby condition
when FSR is TTL-low for five frames or longer. The device enters a production test-mode condition
when either FSR or FSX is held high for five frames or longer (digital).
FSX
12
20
I
Frame synchronization clock input for the transmit channel. FSX operates independently of FSR, but
also in an analogous manner to FSR. The transmit channel enters the standby condition when FSX
is low for five frames or longer. The device enters a production test-mode condition when either FSX
or FSR is held high for five frames or longer (digital).
GND
16
—
Ground return for all internal circuits
LINSEL
15
26
I
Linear selection input. When low, LINSEL selects linear coding/decoding. When high, LINSEL selects
companded coding/decoding. Companding code on the ’AC36 is
μ
-law, and companding code on the
’AC37 is A-law (digital).
MICBIAS
20
42
O
Microphone bias. MICBIAS voltage for the electret microphone is equal to VMID.
MICGS
19
41
O
Output of the internal microphone amplifier. MICGS is used as the feedback to set the microphone
amplifier gain. If sidetone is required, it is accomplished by connecting a series network between
MICGS and EARGS (analog).
MICIN
18
40
I
Microphone input. Electret microphone input to the internal microphone amplifier (analog)
MICMUTE
6
11
I
Microphone input mute control signal. When MICMUTE is active (low), zero code is transmitted (dig.).
PDN
1
43
I
Power-down input. When PDN is low, the device powers down to reduce power consumption (digital).
TSX/DCLKX
14
22
I/O
Transmit time slot strobe (active-low output) or data clock (input) for the transmit channel. In the
fixed-data-rate mode, TSX/DCLKX is an open-drain output that pulls to ground and is used as an
enable signal for a 3-state buffer. In the variable-data-rate mode, DCLKX becomes the transmit data
clock input (digital).
VCC
VMID
5
—
5-V supply voltage for all internal circuits
VCC/2 bias voltage reference. A pair of external, low-leakage, high-frequency capacitors (1
μ
F and
470 pF) should be connected between VMID and ground for filtering.
17
36
O
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