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參數(shù)資料
| 型號(hào)： | TCM129C16 |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | Codec |
| 英文描述： | Single-Chip PCM Codecs And Filters(組合編碼譯碼器/濾波器) |
| 中文描述： | 單芯片的PCM編解碼器和過濾器（組合編碼譯碼器/濾波器） |
| 文件頁數(shù)： | 11/25頁 |
| 文件大?。?/td> | 556K |
| 代理商： | TCM129C16 |
TCM29C13, TCM29C14, TCM29C16, TCM29C17,
TCM129C13, TCM129C14, TCM129C16, TCM129C17
COMBINED SINGLE-CHIP PCM CODEC AND FILTER
SCTS011G – APRIL 1986 – REVISED JULY 1996
11
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
receive timing requirements over recommended ranges of supply voltages and operating free-air
temperature, variable-data-rate mode (see Figure 6)
PARAMETER
MIN
MAX
UNIT
td(TSDR)
td(FSR)
tsu(PCM IN)
th(PCM IN)
tc(DCLKR)
tSER
NOTE 9: tFSLR minimum requirement overrides the td(TSDR) maximum requirement for 64-kHz operation.
Time-slot delay time from DCLKR (see Note 9)
140
td(DCLKR)–140
tc(CLK)–100
ns
Frame-sync delay time
100
ns
Setup time before bit 3 falling edge
10
ns
Hold time after bit 4 falling edge
60
ns
Data clock period
488
15620
ns
Time-slot end receive time
0
ns
64-kbit operation timing requirements over recommended ranges of supply voltage and operating free-air
temperature, variable-data-rate mode
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
tFSLX
tFSLR
tw(DCLK)
Transmit frame-sync minimum down time
FSX = TTL high for remainder of frame
488
ns
Receive frame-sync minimum down time
FSR = TTL high for remainder of frame
1952
ns
μ
s
Pulse duration, data clock
10
switching characteristics
propagation delay times over recommended ranges of supply voltage and operating free-air temperature,
fixed-data-rate mode (see Figures 3 and 4)
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
tpd1
From rising edge of transmit clock to bit 1 data valid at PCM OUT (data enable
time on time-slot entry) (see Note 10)
CL = 0 to 100 pF
0
145
ns
tpd2
From rising edge of transmit clock bit n to bit n data valid at PCM OUT (data
valid time)
CL = 0 to 100 pF
0
145
ns
tpd3
From falling edge of transmit clock bit 8 to bit 8 Hi-Z at PCM OUT (data float time
on time-slot exit) (see Note 10)
CL = 0
60
215
ns
tpd4
From rising edge of transmit clock bit 1 to TSX active (low) (time-slot enable
time)
CL = 0 to 100 pF
0
145
ns
tpd5
From falling edge of transmit clock bit 8 to TSX inactive (high) (time-slot disable
time) (see Note 10)
CL = 0
60
190
ns
tpd6
From rising edge of channel time slot to SIGR update (TCM129C14 and
TCM29C14 only)
0
2
μ
s
NOTE 10: Timing parameters tpd1, tpd3, and tpd5 are referenced to the high-impedance state.
propagation delay times over recommended ranges of operating conditions, variable-data-rate mode (see
Note 11 and Figure 5)
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
tpd7
tpd8
tpd9
tpd10
NOTE 11: Timing parameters tpd8 and tpd9 are referenced to a high-impedance state.
Data delay time from DCLKX
CL = 0 to 100 pF
CL = 0 to 100 pF
CL = 0 to 100 pF
td(TSDX) = 80 ns
0
100
ns
Data delay time from time-slot enable to PCM OUT
0
50
ns
Data delay time from time-slot disable to PCM OUT
0
80
ns
Data delay time from FSX
0
140
ns
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| TCM320AC36DW | VOICE-BAND AUDIO PROCESSORS VBAPE |
| TCM320AC36N | VOICE-BAND AUDIO PROCESSORS VBAPE |
| TCM320AC36PT | VOICE-BAND AUDIO PROCESSORS VBAPE |
| TCM320AC37DW | VOICE-BAND AUDIO PROCESSORS VBAPE |
| TCM320AC37N | VOICE-BAND AUDIO PROCESSORS VBAPE |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TCM129C16A | 制造商:TI 制造商全稱:Texas Instruments 功能描述:COMBINED SINGLE-CHIP PCM CODEC AND FILTER |
| TCM129C16ADW | 制造商:TI 制造商全稱:Texas Instruments 功能描述:COMBINED SINGLE-CHIP PCM CODEC AND FILTER |
| TCM129C16AN | 制造商:TI 制造商全稱:Texas Instruments 功能描述:COMBINED SINGLE-CHIP PCM CODEC AND FILTER |
| TCM129C16DW | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| TCM129C16N | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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