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參數(shù)資料
| 型號(hào)： | TCM129C14 |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | Codec |
| 英文描述： | Single-Chip PCM Codecs And Filters(組合編碼譯碼器/濾波器，模擬環(huán)路) |
| 中文描述： | 單芯片的PCM編解碼器和過濾器（組合編碼譯碼器/濾波器，模擬環(huán)路） |
| 文件頁數(shù)： | 10/25頁 |
| 文件大?。?/td> | 556K |
| 代理商： | TCM129C14 |
TCM29C13, TCM29C14, TCM29C16, TCM29C17,
TCM129C13, TCM129C14, TCM129C16, TCM129C17
COMBINED SINGLE-CHIP PCM CODEC AND FILTER
SCTS011G – APRIL 1986 – REVISED JULY 1996
10
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
receive filter transfer over recommended ranges of supply voltage and operating free-air
temperature (see Figure 2)
PARAMETER
TEST CONDITIONS
MIN
MAX
0.15
UNIT
G i
Gain relative to gain at 1.02 kHz
l i
l i
l i
1 02 kH
1 02 kH
1 02 kH
Input signal at PCM IN is 0 dBm0
PCM IN i 0 dB 0
PCM IN i 0 dB 0
PCM IN i 0 dB 0
f < 200 Hz
dB
f = 200 Hz
–0.5
0.15
f = 300 Hz to 3 kHz
–0.15
0.15
f = 3.3 kHz
–0.35
0.15
f = 3.4 kHz
–1
–0.1
f = 4 kHz
f
4.6 kHz
–14
–30
timing requirements
clock timing requirements over recommended ranges of supply voltage and operating free-air temperature
(see Figures 3 and 4)
MIN
TYP
MAX
UNIT
tc(CLK)
tr, tf
tw(CLK)
tw(DCLK)
Clock period for CLKX, CLKR (2.048-MHz systems)
488
ns
Rise and fall times for CLKX and CLKR
5
30
ns
Pulse duration for CLKX and CLKR (see Note 7)
220
ns
Pulse duration, DCLK (fDCLK = 64 kHz to 2.048 MHz) (see Note 7)
Clock duty cycle, [tw(CLK)/tc(CLK)] for CLKX and CLKR
All typical values are at VBB = –5 V, VCC = 5 V, and TA = 25
°
C.
NOTE 7: FSX CLK must be phase locked with CLKX. FSR CLK must be phase locked with CLKR.
220
ns
45%
50%
55%
transmit timing requirements over recommended ranges of supply voltage and operating free-air
temperature, fixed-data-rate mode (see Figure 3)
MIN
MAX
UNIT
td(FSX)
tsu(SIGX)
th(SIGX)
Frame-sync delay time
100
tc(CLK) –100
ns
Setup time before bit 7 falling edge of CLKX (TMC29C14 and TCM129C14 only)
0
ns
Hold time after bit 8 falling edge of CLKX (TCM29C13 and TCM129C14 only)
0
ns
receive timing requirements over recommended ranges of supply voltages and operating free-air
temperature, fixed-data-rate mode (see Figure 4)
PARAMETER
MIN
MAX
UNIT
td(FSR)
tsu(PCM IN)
th(PCM IN)
Frame-sync delay time
100
tc(CLK)–100
ns
Setup time before bit 1 falling edge (TCM129C14 and TCM29C14 only)
10
ns
Hold time after bit 1 falling edge (TCM129C14 and TCM29C14 only)
60
ns
transmit timing requirements over recommended ranges of supply voltage and operating free-air
temperature, fixed-data-rate mode (see Figure 5)
PARAMETER
MIN
MAX
UNIT
td(TSDX)
td(FSX)
tc(DCLKX)
NOTE 8: tFSLX minimum requirement overrides the td(TSDX) maximum requirement for 64-kHz operation.
Time-slot delay time from DCLKX (see Note 8)
140
td(DCLKX)–140
tc(CLK)–100
15620
ns
Frame-sync delay time
100
ns
Clock period for DCLKX
488
ns
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TCM129C14DW | 制造商:TI 制造商全稱:Texas Instruments 功能描述:COMBINED SINGLE-CHIP PCM CODEC AND FILTER |
| TCM129C16 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:COMBINED SINGLE-CHIP PCM CODEC AND FILTER |
| TCM129C16A | 制造商:TI 制造商全稱:Texas Instruments 功能描述:COMBINED SINGLE-CHIP PCM CODEC AND FILTER |
| TCM129C16ADW | 制造商:TI 制造商全稱:Texas Instruments 功能描述:COMBINED SINGLE-CHIP PCM CODEC AND FILTER |
| TCM129C16AN | 制造商:TI 制造商全稱:Texas Instruments 功能描述:COMBINED SINGLE-CHIP PCM CODEC AND FILTER |
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