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參數(shù)資料
| 型號(hào)： | TC94A04AFD |
| 廠商： | Toshiba Corporation |
| 英文描述： | 1 CHIP AUDIO DIGITAL PROCESSOR |
| 中文描述： | 1芯片音頻數(shù)字處理器 |
| 文件頁數(shù)： | 8/42頁 |
| 文件大?。?/td> | 565K |
| 代理商： | TC94A04AFD |
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TC94A04AF/AFD
2001-11-15
8
2. Microcontroller Interface
2.1
Standard Transmission Mode
When I2CS
=
“L”, data can be transmitted or received in Standard Transmission mode.
When the CS signal is Low, control from the microcontroller is enabled.
The IFCK signal is the transmit/receive clock.
The IFDI signal is the data. The TC94A04AF/AFD loads the IFDI signal on the IFCK signal rising
edge.
When CS
=
“H”, the IFCK and IFDI signals are don’t care.
2.1.1 Setting Resisters
The registers are set by command using the IFDI signals.
The first byte is a command, which differs for each register. The data sent after that are fixed to
two bytes. Both command and data are sent starting from the MSB.
Data are loaded the rising edge of the IFCK signal. Note that commands or data that must be
switched, such as the RUN-MUTE command (command-44h) or the IFF flag (command-4Ah), must be
synchronized with the SYNC signal and loaded on that signal.
IFCK
CS
D11
D10
D13
D12
D15
D14
IFDI
D9
D8
C3
C2
C5
C4
C7
C6
C1
C0
D3
D2
D5
D4
D7
D6
D1
D0
Don’t care
Don’t care
Cn: COMMAND
Dn: Data
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