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參數(shù)資料
| 型號(hào)： | TC94A04AFD |
| 廠商： | Toshiba Corporation |
| 英文描述： | 1 CHIP AUDIO DIGITAL PROCESSOR |
| 中文描述： | 1芯片音頻數(shù)字處理器 |
| 文件頁(yè)數(shù)： | 35/42頁(yè) |
| 文件大?。?/td> | 565K |
| 代理商： | TC94A04AFD |
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TC94A04AF/AFD
2001-11-15
35
Microcontroller Interface
(1)
Standard transmission mode (CS , IFCK, IFDI, IFDO)
Characteristics
Symbol
Test
Circuit
Test Condition
Min
Typ.
Max
Unit
Standby time
t
STB
1.0
μ
s
CS
↓
-IFCK
↓
setup time
t
CCD
0.2
μ
s
IFCK “L” cycle width
t
WLC
0.25
μ
s
IFCK “H” cycle width
t
WHC
0.25
μ
s
IFCK
↑
-
CS
↑
setup time
t
CKC
0.25
μ
s
CS
“H” cycle width
t
WCS
(Note 16)
0.5
μ
s
IFDI-IFCK
↑
setup time
t
SCD
0.2
μ
s
IFCK
↑
-IFDI holed time
t
HCD
0.2
μ
s
IFCK
↓
-IFDO propagation delay time
t
DDO
C
L
=
30 pF
0.2
μ
s
Note 16: The command which is “Sync” in the transfer Sync with Sync signal of a 14 page table 1 control command
table needs to set the CS
=
H section to a minimum of 1 fs more until it transmits the follwing command.
(It needs more than 22.68
μ
s at fs
=
44.1 KHz.)
(2)
I
2
C mode (CS , IFCK, IFDI)
Characteristics
Symbol
Test
Circuit
Test Condition
Min
Typ.
Max
Unit
IFCK clock frequency
t
IFCK
C
L
=
400 pF
0
400
kHz
IFCK “H” cycle width
t
H
C
L
=
400 pF
0.6
μ
s
IFCK “L” cycle width
t
L
C
L
=
400 pF
1.3
μ
s
Data setup time
t
DS
C
L
=
400 pF
0.1
μ
s
Data hold time
t
DH
C
L
=
400 pF
0
μ
s
Transmission start condition hold time
t
SCH
C
L
=
400 pF
0.6
μ
s
Repeat transmission start setup time
t
SCS
C
L
=
400 pF
0.6
μ
s
Transmission end condition
setup time
t
ECS
C
L
=
400 pF
0.6
μ
s
Data transmission interval
I
2
C rising time
I
2
C falling time
t
BUF
C
L
=
400 pF
1.3
μ
s
t
R
t
F
C
L
=
400 pF
0.3
μ
s
C
L
=
400 pF
0.3
μ
s
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