參數(shù)資料
型號(hào): TC9204M
廠商: Electronic Theatre Controls, Inc.
英文描述: 4-Port 10/100/1000 Smart Ethernet Switch
中文描述: 4端口10/100/1000智能以太網(wǎng)交換機(jī)
文件頁數(shù): 12/49頁
文件大小: 1549K
代理商: TC9204M
TC9204M
Preliminary Data Sheet
Pin Listing
(continued)
No.
165
Pin label
Txd40
Priclass40
Type
I/O
pd
Description
GMII/MII transmit data - least significant bit
Priority class - least significant bit. Sets priority level per port basis.
PriClass[4] - '00' - port 4 low priority
PriClass[4] - '01' - port 4 has normal priority
PriClass[4] - '10' - port 4 has high priority
PriClass[4] - '11' - port 4 has very high priority
PriClass[4] is latched on reset
GMII/MII transmit enable
If this pin is set to '1' then all frames with 802.1D Reserved Group
Address or 802.3x Full Duplex PAUSE operation DA will be filtered
out. This setting is provided for testing purposes only and it is
recommended to set high during normal operation.
RejRDA is latched on reset.
GMII transmit clock
Digital +3.3V power supply for I/O
I/O
pd
Transmit Error
I
MII transmit clock
I
s
MII carrier sense indication
I
s
MII collision indication
I
s
Receive Error
G
Digital ground for I/O
I
MII receive clock
I
s
GMII/MII data valid
I
s
GMII receive data - least significant nibble.
MII receive data
I
s
GMII receive data - least significant nibble.
MII receive data
I
s
GMII receive data - least significant nibble.
MII receive data
I
s
GMII receive data - least significant nibble.
MII receive data
I
s
GMII receive data - most significant nibble
I
s
GMII receive data - most significant nibble
I
s
GMII receive data - most significant nibble
I
s
GMII receive data - most significant nibble
P
Digital +3.3V power supply for I/O
I/O
pd
During the normal operation, the backpressure process is executed
until flow control condition disappears or until the time limit for
backpressure is reached. The backpressure time limit is based in the
EEPROM’s
BPTimeValue
register.
When this configuration is ‘0’ the backpressure process will also be
limited from exceeding 28-consecutive collisions. The default value
(28) can be changed in the EEPROM settings.
FullBp is latched upon reset
Txen4
RejRDA
166
I/O
pd
167 gtxclk4
168 Vdd 3.3
169 Txer4
170 Txclk4
171 Crs4
172 Col4
173 Rxer4
174 Vss 3.3
175 Rxclk4
176 Rxdv4
177 Rxd40
O
P
178 Rxd41
179 Rxd42
180 Rxd43
181 Rxd44
182 Rxd45
183 Rxd46
184 Rxd47
185 Vdd 3.3
186 FullBp
Confidential.
Copyright
2003, IC Plus Corp.
12/49
July 29, 2003
TC9204M-DS-R05
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