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參數(shù)資料
| 型號(hào)： | TC55VEM208ASTN55 |
| 廠商： | Toshiba Corporation |
| 英文描述： | TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS |
| 中文描述： | 東芝馬鞍山數(shù)字集成電路硅柵CMOS |
| 文件頁(yè)數(shù)： | 9/11頁(yè) |
| 文件大?。?/td> | 173K |
| 代理商： | TC55VEM208ASTN55 |
TC55VEM208ASTN40,55
2002-08-07 9/11
DATA RETENTION CHARACTERISTICS
(Ta
=
40
°
to 85
°
C)
SYMBOL
PARAMETER
MIN
TYP
MAX
UNIT
V
DH
Data Retention Supply Voltage
1.5
3.6
V
V
DH
=
3.6 V Ta
=
40~85
°
C
10
Ta
=
40~40
°
C
2
I
DDS2
Standby Current
V
DH
=
3.0 V
Ta
=
40~85
°
C
5
μ
A
t
CDR
Chip Deselect to Data Retention Mode Time
0
ns
t
R
Recovery Time
5
ms
CE
Note: When CE is operating at the V
IH
(min.) level, the operating current is given by I
DDS1
during the transition
of V
DD
from 2.3(2.7) to 2.2V(2.4 V).
V
DD
2.3 V
GND
V
IH
DATA RETENTION MODE
t
R
(See Note)
(See Note)
t
CDR
V
DD
0.2 V
CE
V
DD
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