參數(shù)資料
型號： TAS3004PFBRG4
廠商： TEXAS INSTRUMENTS INC
元件分類： 消費家電
英文描述： SPECIALTY CONSUMER CIRCUIT, PQFP48
封裝： GREEN, PLASTIC, TQFP-48
文件頁數(shù)： 7/84頁
文件大?。?/td> 671K
代理商： TAS3004PFBRG4
2–2
2.2
ADC Digital Output Modes
ADC digital output mode (SDOUT0) has two operational modes, normal and monaural. In the normal mode, the
output of the ADC conforms to the output modes described in Sections 2.2.1 through 2.2.3. To enter the normal output
mode, bit 7 (ADM) in the analog control register must be cleared to 0. In the monaural output mode, the digital output
of the ADC conforms to the output modes described in Sections 2.3.1 through 2.3.6. To enter the monaural mode,
bit 7 (ADM) in the analog control register must be set to 1.
2.2.1
MSB First, Right-Justified Serial Interface Format—Normal Mode
The normal output mode for the MSB first, right-justified serial interface format is for 16, 18, 20, and 24 bits with bit 7
(ADM) in the analog control register cleared to 0. Figure 2–1 shows the following characteristics of this protocol:
Left channel is transmitted when LRCLK is high.
The SDIN(s) (recorded) data is justified to the trailing edge of the LRCLK.
The SDOUT(s) MSB (playback) data is transmitted at the same time as LRCLK edge and captured at the
next rising edge of SCLK.
If LRCLK phase changes by more than 10MCLK, the codec automatically resets.
SCLK
LRCLK = fS
MSB
LSB
……
…… MSB
LSB
……
SDIN
MSB
LSB
……
…… MSB
LSB
……
Left Channel
Right Channel
SDOUT
……
Figure 2–1. MSB First, Right-Justified Serial Interface Format—Normal Mode
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