參數(shù)資料
型號(hào)： TAS3002
廠商： TEXAS INSTRUMENTS INC
元件分類： 消費(fèi)家電
英文描述： SPECIALTY CONSUMER CIRCUIT, PQFP48
封裝： QFP-48
文件頁(yè)數(shù)： 30/54頁(yè)
文件大?。?/td> 266K
代理商： TAS3002
72
Clears all the registers in the circuits
Purges the codec
Selects analog input A (RINA and LINA) and sets the input A active indicator (INPA) low
Initializes the equalization parameters to AllPass filters
Sets the digital audio interface to the I2S 18-bit mode
Sets the bass/treble to 0 dB
Sets the mixer gain to 0 dB SDIN1 and mutes both SDIN2 and analog-in
Sets the volume to –40 dB
Turns off all enhancement features (DRCE, etc.)
Reads the I2C address. If the address is 68h, the device reads its EEPROM. It is possible to load the
user-defined bass/treble data and break points (optional). If there is no data, the device loads default
bass/treble delta and break points from ROM.
If the address is 6Ah, the device puts the I2C interface in slave mode and waits for input.
7.2.3
Reset Circuit
Because the TAS3002 device has an internal power-on reset (POR), in many cases, additional components are not
needed to reset the device. It resets internally at approximately 80% of VDD.
In the case where the system power supplies are slow in reaching their final voltage or where there is a difference
in the time the system power supplies take to become stable, the TAS3002 reset can be delayed by a simple RC
circuit.
0.1
F
DVDD
6
TAS3002
RESET
10 k
DVSS
Figure 71. TAS3002 Reset Circuit
The reset delay for the above circuit can be calculated by the simple equation:
trd = 0.8RC + 400 s
Where:
trd = The delay before the TAS3002 device comes out of reset
C = Value of the capacitance from RESET (pin 6) to DVSS
R = Value of the resistance from RESET (pin 6) to DVDD
The circuit described in Figure 71 delays the start-up of the TAS3002 device approximately 1.2 ms.
When it is necessary to control the reset of the TAS3002 device with an external device, such as a microcontroller,
RESET (pin 6) can be treated as a logic signal. It then brings the device out of reset when the voltage on RESET
reaches VDD/2.
7.2.4
Fast Load Mode
While in fast load mode—FL bit (bit 7 of main control register 1) = 0—it is possible to update the parametric
equalization without any audio processing delay. The audio processor pauses while the RAM is updated in this mode.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
TAS3002PFB 功能描述:音頻 DSP Digital Audio Processor w/ Codec RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風(fēng)格: 封裝 / 箱體: 封裝:Tube
TAS3002PFBG4 功能描述:音頻 DSP Digital Audio Processor w/ Codec RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風(fēng)格: 封裝 / 箱體: 封裝:Tube
TAS3002PFBR 功能描述:音頻 DSP Digital Audio Processor w/ Codec RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風(fēng)格: 封裝 / 箱體: 封裝:Tube
TAS3002PFBRG4 功能描述:音頻 DSP Digital Audio Processor w/ Codec RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風(fēng)格: 封裝 / 箱體: 封裝:Tube
TAS3004 制造商:TI 制造商全稱:Texas Instruments 功能描述:Digital Audio Processor With Codec
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