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參數資料
| 型號： | T8xC51SND1 |
| 廠商： | Atmel Corp. |
| 英文描述： | Single Chip Microcontroller with MP3 Decoder and Man Machine Interface |
| 中文描述： | 單芯片微控制器，帶有MP3解碼器和人機界面 |
| 文件頁數： | 30/60頁 |
| 文件大小： | 868K |
| 代理商： | T8XC51SND1 |
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30
T8xC51SND1
Rev. D
–
15-Nov-01
9. Peripherals
The T8xC51SND1 peripherals are briefly described in the following sections. For further
details on how to interface (hardware and software) to these peripherals, please refer to
the T8xC51SND1 design guide.
9.1 Clock Generator System
The T8xC51SND1 internal clocks are extracted from an on-chip PLL fed by an on-chip
oscillator. Four clocks are generated respectively for the C51 core, the MP3 decoder,
the audio interface, and the other peripherals. The C51 and peripheral clocks are
derived from the oscillator clock. The MP3 decoder clock is generated by dividing the
PLL output clock. The audio interface sample rates are also obtained by dividing the
PLL output clock.
9.2 Ports
The T8xC51SND1 implements five 8-bit ports (P0 to P4) and one 4-bit port (P5). In addi-
tion to performing general-purpose I/O, some ports are capable of external data memory
operations; others allow for alternate functions. All I/O Ports are bidirectional. Each Port
contains a latch, an output driver and an input buffer. Port 0 and Port 2 output drivers
and input buffers facilitate external memory operations. Some Port 1, Port 3 and Port 4
pins serve for both general-purpose I/O and alternate functions.
9.3 Timers/Counters
The T8xC51SND1 implements the two general-purpose, 16-bit Timers/Counters of a
standard C51. They are identified as Timer 0, Timer 1, and can independently be config-
ured each to operate in a variety of modes as a Timer or as an event Counter. When
operating as a Timer, a Timer/Counter runs for a programmed length of time, then
issues an interrupt request. When operating as a Counter, a Timer/Counter counts neg-
ative transitions on an external pin. After a preset number of counts, the Counter issues
an interrupt request.
9.4 Watchdog Timer
The T8xC51SND1 implements a hardware Watchdog Timer that automatically resets
the chip if it is allowed to time out. The WDT provides a means of recovering from rou-
tines that do not complete successfully due to software or hardware malfunctions.
9.5 MP3 Decoder
The T8xC51SND1 implements a MPEG I/II audio layer 3 decoder (known as MP3
decoder).
In MPEG I (ISO 11172-3) three layers of compression have been standardized support-
ing three sampling frequencies: 48, 44.1, and 32 KHz. Among these layers, layer 3
allows highest compression rate of about 12:1 while still maintaining CD audio quality.
For example, 3 minutes of CD audio (16-bit PCM, 44.1 KHz) data, which needs about 32
MBytes of storage, can be encoded into only 2.7 MBytes of MPEG I audio layer 3 data.
In MPEG II (ISO 13818-3), three additional sampling frequencies: 24, 22.05, and 16
KHz are supported for low bit rates applications.
The T8xC51SND1 can decode in real-time the MPEG I audio layer 3 encoded data into
a PCM audio data, and also supports MPEG II audio layer 3 additional frequencies.
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