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參數(shù)資料
| 型號： | T8xC51SND1 |
| 廠商： | Atmel Corp. |
| 英文描述： | Single Chip Microcontroller with MP3 Decoder and Man Machine Interface |
| 中文描述： | 單芯片微控制器，帶有MP3解碼器和人機界面 |
| 文件頁數(shù)： | 15/60頁 |
| 文件大小： | 868K |
| 代理商： | T8XC51SND1 |
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15
T8xC51SND1
Rev. D
–
15-Nov-01
7. Address Spaces
The T8xC51SND1 derivatives implement four different address spaces:
Program/Code Memory
Boot Memory
Data Memory
Special Function Registers (SFRs)
7.1 Code Memory
The T89C51SND1 and T83C51SND1 implement 64 Kbytes of on-chip program/code
memory. The T83C51SND1 product provides the internal program/code memory in
ROM technology while the T89C51SND1 product provides it in FLASH technology.
The FLASH memory increases EPROM and ROM functionality by in-circuit electrical
erasure and programming. Thanks to the internal charge pump, the high voltage needed
for programming or erasing FLASH cells is generated on-chip using the standard VDD
voltage. Thus, the T89C51SND1 can be programmed using only one voltage and allows
in application software programming commonly known as IAP. Hardware programming
mode is also available using specific programming tool.
7.2 Boot Memory
The T89C51SND1 implements 4 Kbytes of on-chip boot memory provided in FLASH
technology. This boot memory is delivered programmed with a standard boot loader
software allowing in system programming commonly known as ISP. It also contains
some Application Programming Interfaces routines commonly known as API allowing
user to develop its own boot loader.
7.3 Data Memory
The T89C51CC01 derivatives implement 2304 bytes of on-chip data RAM. This memory
is divided in two separate areas:
256 bytes of on-chip RAM memory (standard C51 memory).
2048 bytes of on-chip expanded RAM memory (ERAM accessible via MOVX
instructions).
7.4 Special Function Registers
The Special Function Registers (SFRs) of the T89C51CC01 derivatives fall into the cat-
egories detailed in Table 16 to Table 32. The relative addresses of these SFRs are
provided together with their reset values in Table 33. In this table, the bit-addressable
registers are identified by Note 1.
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