參數(shù)資料
型號(hào)： T89C51RD2-DDFI-L
廠商： Atmel Corp.
英文描述： IC - OPTOISOLATOR 4N28
中文描述： 0至40MHz可編程閃存8位微控制器
文件頁數(shù)： 82/170頁
文件大?。?/td> 1927K
代理商： T89C51RD2-DDFI-L
82
A/T89C51CC01
4129L–CAN–08/05
Bit Shortening
If, on the other hand, the transmitter oscillator is faster than the receiver one, the next
falling edge used for resynchronization may be too early. So Phase Segment 2 in bit N
is shortened in order to adjust the sample point for bit N+1 and the end of the bit time
Synchronization Jump Width
The limit to the amount of lengthening or shortening of the Phase Segments is set by the
Resynchronization Jump Width.
This segment may not be longer than Phase Segment 2.
Programming the Sample Point
Programming of the sample point allows "tuning" of the characteristics to suit the bus.
Early sampling allows more Time Quanta in the Phase Segment 2 so the Synchroniza-
tion Jump Width can be programmed to its maximum. This maximum capacity to
shorten or lengthen the bit time decreases the sensitivity to node oscillator tolerances,
so that lower cost oscillators such as ceramic resonators may be used.
Late sampling allows more Time Quanta in the Propagation Time Segment which allows
a poorer bus topology and maximum bus length.
Arbitration
Figure 42.
Bus Arbitration
The CAN protocol handles bus accesses according to the concept called “Carrier Sense
Multiple Access with Arbitration on Message Priority”.
During transmission, arbitration on the CAN bus can be lost to a competing device with
a higher priority CAN Identifier. This arbitration concept avoids collisions of messages
whose transmission was started by more than one node simultaneously and makes sure
the most important message is sent first without time loss.
The bus access conflict is resolved during the arbitration field mostly over the identifier
value. If a data frame and a remote frame with the same identifier are initiated at the
same time, the data frame prevails over the remote frame (c.f. RTR bit).
Errors
The CAN protocol signals any errors immediately as they occur. Three error detection
mechanisms are implemented at the message level and two at the bit level:
Error at Message Level
Cyclic Redundancy Check (CRC)
The CRC safeguards the information in the frame by adding redundant check bits at
the transmission end. At the receiver these bits are re-computed and tested against
the received bits. If they do not agree there has been a CRC error.
Frame Check
This mechanism verifies the structure of the transmitted frame by checking the bit
fields against the fixed format and the frame size. Errors detected by frame checks
are designated "format errors".
node A
TXCAN
node B
TXCAN
ID10 ID9
ID8
ID7
ID6
ID5
ID4
ID3
ID2
ID1
ID0
SOF
RTR IDE
CAN bus
- - - - - - - - -
Arbitration lost
Node A loses the bus
Node B wins the bus
相關(guān)PDF資料
PDF描述
T89C51RD2-DDFI-M 0 to 40MHz Flash Programmable 8-bit Microcontroller
T89C51RD2-DDSC-L 0 to 40MHz Flash Programmable 8-bit Microcontroller
T89C51RD2-DDSC-M 0 to 40MHz Flash Programmable 8-bit Microcontroller
T89C51RD2-DDSI-L 0 to 40MHz Flash Programmable 8-bit Microcontroller
T89C51RD2-DDSI-M 0 to 40MHz Flash Programmable 8-bit Microcontroller
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
T89C51RD2-DDFI-M 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:0 to 40MHz Flash Programmable 8-bit Microcontroller
T89C51RD2-DDRC-L 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:0 to 40MHz Flash Programmable 8-bit Microcontroller
T89C51RD2-DDRC-M 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:0 to 40MHz Flash Programmable 8-bit Microcontroller
T89C51RD2-DDRI-L 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:0 to 40MHz Flash Programmable 8-bit Microcontroller
T89C51RD2-DDRI-M 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:0 to 40MHz Flash Programmable 8-bit Microcontroller
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