參數(shù)資料
型號(hào)： T89C51RC2-SLBCL
廠商： Atmel Corp.
英文描述： 8-bit Microcontroller with 16 Kbytes/ 32 Kbytes FLASH
中文描述： 8位微控制器，帶有16字節(jié)/ 32千字節(jié)閃存
文件頁數(shù)： 149/170頁
文件大?。?/td> 1927K
代理商： T89C51RC2-SLBCL
149
A/T89C51CC01
4129L–CAN–08/05
Notes:
1. Operating I
CC
is measured with all output pins disconnected; XTAL1 driven with
T
CLCH
, T
CHCL
= 5 ns (see Figure 67.), V
IL
= V
SS
+ 0.5V,
V
IH
= V
CC
- 0.5V; XTAL2 N.C.; EA = RST = Port 0 = V
CC
. I
CC
would be slightly higher
if a crystal oscillator used (see Figure 64.).
2. Idle I
CC
is measured with all output pins disconnected; XTAL1 driven with T
CLCH
,
T
CHCL
= 5 ns, V
IL
= V
SS
+ 0.5V, V
IH
= V
CC
- 0.5V; XTAL2 N.C; Port 0 = V
CC
; EA = RST
= V
SS
(see Figure 65.).
3. Power-down I
CC
is measured with all output pins disconnected; EA = V
CC
, PORT 0 =
V
CC
; XTAL2 NC.; RST = V
SS
(see Figure 66.). In addition, the WDT must be inactive
and the POF flag must be set.
4. Capacitance loading on Ports 0 and 2 may cause spurious noise pulses to be super-
imposed on the V
OL
s of ALE and Ports 1 and 3. The noise is due to external bus
capacitance discharging into the Port 0 and Port 2 pins when these pins make 1 to 0
transitions during bus operation. In the worst cases (capacitive loading 100pF), the
noise pulse on the ALE line may exceed 0.45V with maxi V
OL
peak 0.6V. A Schmitt
Trigger use is not necessary.
5. Typicals are based on a limited number of samples and are not guaranteed. The val-
ues listed are at room temperature.
6. Under steady state (non-transient) conditions, I
OL
must be externally limited as fol-
lows:
Maximum I
OL
per port pin: 10 mA
Maximum I
OL
per 8-bit port:
Port 0: 26 mA
Ports 1, 2 and 3: 15 mA
Maximum total I
OL
for all output pins: 71 mA
If I
OL
exceeds the test condition, V
OL
may exceed the related specification. Pins are
not guaranteed to sink current greater than the listed test conditions.
7. ICC_FLASH_WRITE operating current while a Flash block write is on going.
8. Flash Retention is guaranteed with the same formula for V
CC
Min down to 0.
Figure 64.
I
CC
Test Condition, Active Mode
EA
V
CC
V
CC
I
CC
(NC)
CLOCK
SIGNAL
V
CC
All other pins are disconnected.
RST
XTAL2
XTAL1
V
SS
V
CC
P0
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