參數(shù)資料
型號: T89C51CC02UA-TDSIM
廠商: ATMEL CORP
元件分類: 微控制器/微處理器
英文描述: AB 9C 3#12 6#16 SKT RECP
中文描述: 8-BIT, FLASH, 40 MHz, MICROCONTROLLER, PDSO24
封裝: 0.300 INCH, PLASTIC, SOIC-24
文件頁數(shù): 39/170頁
文件大?。?/td> 1927K
代理商: T89C51CC02UA-TDSIM
39
A/T89C51CC01
4129L–CAN–08/05
FM0 Memory Architecture
The Flash memory is made up of 4 blocks (see Figure 20):
The memory array (user space) 32K Bytes
The Extra Row
The Hardware security bits
The column latch registers
User Space
This space is composed of a 32K Bytes Flash memory organized in 256 pages of 128
Bytes. It contains the user’s application code.
Extra Row (XRow)
This row is a part of FM0 and has a size of 128 Bytes. The extra row may contain infor-
mation for boot loader usage.
Hardware Security Byte
The Hardware security Byte space is a part of FM0 and has a size of 1 byte.
The 4 MSB can be read/written by software, the 4 LSB can only be read by software and
written by hardware in parallel mode.
Column Latches
The column latches, also part of FM0, have a size of full page (128 Bytes).
The column latches are the entrance buffers of the three previous memory locations
(user array, XROW and Hardware security byte).
Cross Flash Memory Access
Description
The FM0 memory can be program only from FM1. Programming FM0 from FM0 or from
external memory is impossible.
The FM1 memory can be program only by parallel programming.
The Table 24 show all software Flash access allowed.
Table 24.
Cross Flash Memory Access
C
Action
FM0
(user Flash)
FM1
(boot Flash)
FM0
(user Flash)
Read
ok
-
Load column latch
ok
-
Write
-
-
FM1
(boot Flash)
Read
ok
ok
Load column latch
ok
-
Write
ok
-
External
memory
EA = 0
Read
-
-
Load column latch
-
-
Write
-
-
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