參數資料
型號: T89C51CC02UA-TDSIM
廠商: ATMEL CORP
元件分類: 微控制器/微處理器
英文描述: AB 9C 3#12 6#16 SKT RECP
中文描述: 8-BIT, FLASH, 40 MHz, MICROCONTROLLER, PDSO24
封裝: 0.300 INCH, PLASTIC, SOIC-24
文件頁數: 141/170頁
文件大?。?/td> 1927K
代理商: T89C51CC02UA-TDSIM
141
A/T89C51CC01
4129L–CAN–08/05
Each of the interrupt sources can be individually enabled or disabled by setting or clear-
ing a bit in the Interrupt Enable register. This register also contains a global disable bit
which must be cleared to disable all the interrupts at the same time.
Each interrupt source can also be individually programmed to one of four priority levels
by setting or clearing a bit in the Interrupt Priority registers. The Table below shows the
bit values and priority levels associated with each combination.
Table 113.
Priority Level Bit Values
A low-priority interrupt can be interrupted by a high priority interrupt but not by another
low-priority interrupt. A high-priority interrupt cannot be interrupted by any other interrupt
source.
If two interrupt requests of different priority levels are received simultaneously, the
request of the higher priority level is serviced. If interrupt requests of the same priority
level are received simultaneously, an internal polling sequence determines which
request is serviced. Thus within each priority level there is a second priority structure
determined by the polling sequence, see Table 114.
Table 114.
Interrupt Priority Within level
IPH.x
IPL.x
Interrupt Level Priority
0
0
0 (Lowest)
0
1
1
1
0
2
1
1
3 (Highest)
Interrupt Name
Interrupt Address Vector
Interrupt Number
Polling Priority
external interrupt (INT0)
0003h
1
1
Timer 0 (TF0)
000Bh
2
2
external interrupt (INT1)
0013h
3
3
Timer 1 (TF1)
001Bh
4
4
PCA (CF or CCFn)
0033h
7
5
UART (RI or TI)
0023h
5
6
Timer 2 (TF2)
002Bh
6
7
CAN (Txok, Rxok, Err or
OvrBuf)
003Bh
8
8
ADC (ADCI)
0043h
9
9
CAN Timer Overflow (OVRTIM)
004Bh
10
10
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