參數(shù)資料
型號: T7906EDD-E
廠商: ATMEL CORP
元件分類: 微控制器/微處理器
英文描述: Single Point to Point IEEE 1355 High Speed Controller
中文描述: 3 CHANNEL(S), 200M bps, SERIAL COMM CONTROLLER, UUC
封裝: DIE
文件頁數(shù): 8/42頁
文件大?。?/td> 339K
代理商: T7906EDD-E
8
T7906E
Rev. A
27-Aug.-01
Note:
1. IOB15-0, IOB21-18: 6 mA
IOB17-16: 8mA
IOB24-22: 3mA
IOB27-25: input only
All inputs have an internal pull-up resistor, with the following exceptions, which have an
internal pull-down resistor: LDI, LSI, TRST*, TMS.
TMR2_CLK
I
timer2 clock (max. 12.5 MHz)
TMR2_EXP.
O
timer2 expired. Asserted for one cycle
if the value of counter2 is equal to the
content of register TPERIOD2(3:0)
3
50
RxD1
I
receive data to UART1
TxD1
O
transmit data from UART1
3
50
LDI
I
Link Data Input
LSI
I
Link Strobe Input
LDO
O
Link Data Output
12
25
LSO
O
Link Strobe Output
12
25
DATA(15:0)
I/O
common T7906E data bus
3
25
GPIO(7:0)
I/O
General purpose input/output lines.
3
25
IOB(27:0)
I/O
Control bus. The T7906E controls the connected
interface via these lines. The function of each control
signal is described in a separate table.
see note (1)
25
TRST*
I
Test Reset. Resets the test state machine.
TCK
I
Test Clock. Provides an asynchronous clock for JTAG
boundary scan
TMS
I
Test Mode Select. Used to control the test state
machine. This input should be left unconnected or tied
to ground during normal operation!
TDI
I
Test Data Input. Provides serial data for the boundary
scan logic
TDO
O/Z
Test Data Output. Serial scan output of the boundary
scan path
3
50
RESET*
I
T7906E Reset. Sets the T7906E to a known state.
This input must be asserted (low) at power-up. The
minimum width of RESET low is 2 cycles when CLK is
running
CLK
I
External clock input to T7906E (max. 5 MHz)
PLLOUT
O
Output of internal PLL. Used to connect a network of
external RC devices
VCC
Power Supply
GND
Ground
Signal
Direction
Description
max. output load
Signal
[mA]
[pF]
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