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參數(shù)資料
| 型號： | T6B70BF |
| 廠商： | Toshiba Corporation |
| 英文描述： | TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic |
| 中文描述： | 東芝的CMOS數(shù)字集成電路硅單片 |
| 文件頁數(shù)： | 4/15頁 |
| 文件大小： | 280K |
| 代理商： | T6B70BF |
T6B70AF
2002-02-28
4
(2)
Amplifier input circuit and signal detection/non-detection circuit (receiving block)
The modulation signal input block incorporates two level comparators having a high and a low
threshold values to detect the external sine wave signal with amplitude higher than the specified
threshold. Thus, it avoids signals with amplitude lower than the specified threshold (e.g., noise
signals) being detected erroneously.
The detection frequency range (frequency window) is determined by the divider ratio 1/18 to 1/14 of
Fosc.
In detection/non-detection determined condition, when the signals within the specified frequency
range are detected (or not detected) sequentially, signals are controlled using the majority rule. The
time which detection/non-detection is determined takes 9 to 15 waves to pass when one wave is
referenced to Fosc/16 frequency.
VH
VL
Input
sensitivity
V
PP
Detect reception
Not detect reception
Not detect reception
Not detect reception
AMPIN input sine waveform
AMPOUT output timing (when
RESET
is Low)
VH
VL
Held at High
Held at Low
VBIAS
VBIAS < VL
VBIAS > VH
VH > VBIAS > VL
VH > VBIAS > VL
AMPOUT
AMPOUT Truth Table
VA
VB
AMPOUT
VBIAS > VH
L
H
L
VH > VBIAS > VL
H
H
Hold
VBIAS < VL
H
L
H
R
R
R
R
V
SS
V
SS
A
A
7
V
Reference
voltage
VH
V
DD
AMPIN pin
Reference
voltage
VL
High comparator
VA
6
AMPOUT pin
9
DOUT
pin
Cycle
measurement
counter
Analog
signal
detection
/non-
detection
circuit
Low comparator
VB
RESET
V
DD
R
Q
S
Q
RESET
VBIAS
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