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參數(shù)資料
| 型號： | T6828-TUS |
| 廠商： | ATMEL CORP |
| 元件分類： | 外設及接口 |
| 英文描述： | Triple Halfbridge DMOS OUTPUT DRIVER WITH SERIAL INPUT CONTROL |
| 中文描述： | HALF BRIDGE BASED PRPHL DRVR, PDSO14 |
| 封裝： | POWER, SO-14 |
| 文件頁數(shù)： | 9/16頁 |
| 文件大小： | 469K |
| 代理商： | T6828-TUS |
9
T6818/T6828
4530C–BCD–11/03
3.6
Thermal shutdown
hysteresis
T
j switch off
15
C
B
3.7
Ratio thermal shutdown
off/thermal prewarning
set
T
j switch off/
T
jPW set
1.05
1.2
B
3.8
Ratio thermal shutdown
on/thermal prewarning
reset
Output Specification (OUT1-OUT3)
T
j switch on/
T
jPW reset
1.05
1.2
B
4
4.1
On resistance
I
Out 1-3
= -1.3 A
2, 12,
13
R
DS On1-3
1.1
A
4.2
I
Out 1-3
= 1.3 A
2, 12,
13
R
DS On1-3
1.1
A
4.3
High-side output
leakage current
V
Out 1-3
= 0 V
,
output stages off
2, 12,
13
I
Out 1-3
-15
μA
A
4.4
Low-side output
leakage current
V
Out 1-3
= V
VS,
output stages off
2, 12,
13
I
Out 1-3
200
μA
A
4.5
High-side switch
reverse diode forward
voltage
I
Out 1-3
= 1.5 A
2, 12,
13
V
Out 1-3
- V
VS
1.5
V
A
4.6
Low-side switch reverse
diode forward voltage
I
Out 1-3
= -1.5 A
2, 12,
13
V
Out 1-3
-1.5
V
A
4.7
High-side overcurrent
limitation and shutdown
threshold
2, 12,
13
I
Out 1-3
-2.5
-2
-1.5
A
A
4.8
Low-side overcurrent
limitation and shutdown
threshold
2, 12,
13
I
Out 1-3
1.5
2
2.5
A
A
4.9
Overcurrent shutdown
delay time
t
dSd
10
40
μs
A
4.10
High-side open-load
detection threshold
2, 12,
13
I
Out1-3
-45
-30
-15
mA
A
4.11
Low-side open-load
detection threshold
2, 12,
13
I
Out1-3
15
30
45
mA
A
4.12
Open-load detection
delay time
t
dSd
200
600
μs
A
4.13
High-side output switch
on delay
(1)
V
VS
= 13 V
R
Load
= 30
V
VS
= 13 V
R
Load
= 30
V
VS
= 13 V
R
Load
= 30
t
don
20
μs
A
4.14
Low-side output switch
on delay
(1)
t
don
20
μs
A
4.15
High-side output switch
off delay
(1)
t
doff
20
μs
A
Electrical Characteristics (Continued)
7.5 V < V
VS
< 40 V; 4.75 V < V
VCC
< 5.25 V; INH = High; -40 C < T
j
< 150 C; unless otherwise specified, all values refer to GND pins.
No.
Parameters
Test Conditions
Pin
Symbol
Min.
Typ.
Max.
Unit
Type*
*) Type means: A =100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Note:
1. Delay time between rising edge of input signal at pin CS after data transmission and switch on output stages to 90% of final
level. Device not in standby for t > 1 ms
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