參數(shù)資料
型號(hào): T6828-TUS
廠商: ATMEL CORP
元件分類: 外設(shè)及接口
英文描述: Triple Halfbridge DMOS OUTPUT DRIVER WITH SERIAL INPUT CONTROL
中文描述: HALF BRIDGE BASED PRPHL DRVR, PDSO14
封裝: POWER, SO-14
文件頁(yè)數(shù): 10/16頁(yè)
文件大小: 469K
代理商: T6828-TUS
10
T6818/T6828
4530C–BCD–11/03
4.16
Low-side output switch
off delay
(1)
V
VS
= 13 V
R
Load
= 30
t
doff
3
μs
A
4.17
Dead time between
corresponding high-
and low-side switches
Logic Inputs DI, CLK, CS, INH
V
VS
= 13 V
R
Load
= 30
t
don
- t
doff
1
μs
A
5
5.1
Input voltage low-level
threshold
4-6, 10
V
IL
0.3
V
VCC
V
A
5.2
Input voltage high-level
threshold
4-6, 10
V
IH
0.7
V
VCC
V
A
5.3
Hysteresis of input
voltage
4-6, 10
V
I
50
700
mV
B
5.4
Pull-down current pin
DI, CLK, INH
V
DI
, V
CLK,
V
INH
= V
CC
5, 6, 10
I
PD
10
65
μA
A
5.5
Pull-up current
Pin CS
Serial Interface – Logic Output DO
V
CS
= 0 V
4
I
PU
-65
-10
μA
A
6
6.1
Output-voltage low level I
DOL
= 2 mA
Output-voltage high
level
9
V
DOL
0.4
V
A
6.2
I
DOL
= -2 mA
9
V
DOH
V
VCC
-
0.7 V
V
A
6.3
Leakage current
(tristate)
V
CS
= V
CC
0V < V
DO
< V
VCC
9
I
DO
-10
10
μA
A
7
Inhibit Input - Timing
7.1
Delay time from
standby to normal
operation
t
dINH
100
μs
A
Electrical Characteristics (Continued)
7.5 V < V
VS
< 40 V; 4.75 V < V
VCC
< 5.25 V; INH = High; -40 C < T
j
< 150 C; unless otherwise specified, all values refer to GND pins.
No.
Parameters
Test Conditions
Pin
Symbol
Min.
Typ.
Max.
Unit
Type*
*) Type means: A =100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Note:
1. Delay time between rising edge of input signal at pin CS after data transmission and switch on output stages to 90% of final
level. Device not in standby for t > 1 ms
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