參數(shù)資料
型號: T6816
廠商: Atmel Corp.
英文描述: 40-V Dual Hex Output Driver with Serial Input Control
中文描述: 40 - V雙六角控制的串行輸入輸出驅(qū)動器
文件頁數(shù): 5/15頁
文件大?。?/td> 171K
代理商: T6816
5
T6816
4595B–BCD–05/03
Table 2.
Output Data Protocol
Output (Status)
Register
Note:
Bit 0 to 15 = high: overtemperature shutdown
13
OLD
Open load detection (low = on)
14
SCT
Programmable time delay for short circuit (shutdown delay high/
low = 12 ms/1.5 ms
15
SI
Software inhibit; low = standby, high = normal operation
(data transfer is not affected by standby function because the
digital part is still powered)
Bit
Function
0
TP
Temperature prewarning: high = warning (overtemperature shut-
down see remark below)
1
Status LS1
Normal operation: high = output is on, low = output is off
Open-load detection: high = open load, low = no open load
(correct load condition is detected if the corresponding output is
switched off)
2
Status HS1
Normal operation: high = output is on, low = output is off
Open-load detection: high = open load, low = no open load
(correct load condition is detected if the corresponding output is
switched off)
3
Status LS2
Description see LS1
4
Status HS2
Description see HS1
5
Status LS3
Description see LS1
6
Status HS3
Description see HS1
7
Status LS4
Description see LS1
8
Status HS4
Description see HS1
9
Status LS5
Description see LS1
10
Status HS5
Description see HS1
11
Status LS6
Description see LS1
12
Status HS6
Description see HS1
13
SCD
Short circuit detected: set high, when at least one output is
switched off by a short circuit condition
14
INH
Inhibit: this bit is controlled by software (bit SI in input register)
and hardware inhibit (Pin 17). High = standby, low = normal
operation
15
PSF
Power supply fail: undervoltage at Pin VS detected
Table 1.
Input Data Protocol (Continued)
Bit
Input Register
Function
Table 3.
Status of the Input Register after Power on Reset
Bit 15
(SI)
Bit 14
(SCT)
Bit 13
(OLD)
Bit 12
(HS6)
Bit 11
(LS6)
Bit 10
(HS5)
Bit 9
(LS5)
Bit 8
(HS4)
Bit 7
(LS4)
Bit 6
(HS3)
Bit 5
(LS3)
Bit 4
(HS2)
Bit 3
(LS2)
Bit 2
(HS1)
Bit 1
(LS1)
Bit 0
(SRR)
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
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