參數(shù)資料
型號: T6816
廠商: Atmel Corp.
英文描述: 40-V Dual Hex Output Driver with Serial Input Control
中文描述: 40 - V雙六角控制的串行輸入輸出驅(qū)動器
文件頁數(shù): 11/15頁
文件大小: 171K
代理商: T6816
11
T6816
4595B–BCD–05/03
Serial Interface — Timing
Parameters
8
Serial Interface - Logic Output DO
8.1
Output voltage low
level
I
OL
= 3 mA
18
V
DOL
0.5
V
A
8.2
Output voltage high
level
I
OL
= -2 mA
18
V
DOH
V
VCC
-
0.7 V
V
A
8.3
Leakage current
(tri-state)
V
CS
= V
VCC,
0 V < V
DO
< V
VCC
18
I
DO
-10
10
μA
A
Electrical Characteristics (Continued)
7.5 V < V
VS
< 40 V; 4.5 V < V
VCC
< 5.5 V; INH = High; -40°C < T
j
< 150°C; unless otherwise specified,
all values refer to GND pins.
No.
Parameters
Test Conditions
Pin
Symbol
Min.
Typ.
Max.
Unit
Type*
*) Type means: A =100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Notes:
1. Delay time between rising edge of CS after data transmission and switch on output stages to 90% of final level
Test Conditions
Timing Chart No.
Symbol
Min.
Typ.
Max.
Unit
DO enable after CS falling edge
C
DO
= 100 pF
C
DO
= 100 pF
C
DO
= 100 pF
C
DO
= 100 pF
C
DO
= 100 pF
1
t
ENDO
t
DISDO
t
DOf
t
DOr
t
DOVal
t
CSSethl
t
CSSetlh
200
ns
DO disable after CS rising edge
2
200
ns
DO fall time
100
ns
DO rise time
100
ns
DO valid time
10
200
ns
CS setup time
4
225
ns
CS setup time
8
225
ns
CS high time
Input register Bit 14
(SCT) = high
9
t
CSh
16
ms
CS high time
Input register Bit 14
(SCT) = low
9
t
CSh
2
ms
CLK high time
5
t
CLKh
t
CLKl
t
CLKp
t
CLKSethl
t
CLKSetlh
t
DIset
t
DIHold
225
ns
CLK low time
6
225
ns
CLK period time
500
ns
CLK setup time
7
225
ns
CLK setup time
3
225
ns
DI setup time
11
40
ns
DI hold time
12
40
ns
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