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參數資料
| 型號： | T15N1024A-70HI |
| 廠商： | TM Technology, Inc. |
| 英文描述： | 128K X 8 LOW POWER CMOS STATIC RAM |
| 中文描述： | 128K的× 8低功耗CMOS靜態(tài)RAM |
| 文件頁數： | 8/13頁 |
| 文件大小： | 91K |
| 代理商： | T15N1024A-70HI |
TE
CH
tm
WRITE CYCLE 1
(
WE
Controlled)
T15N1024A
TM Technology Inc. reserves the right
P. 8
to change products or specifications without notice.
Publication Date: FEB. 2003
Revision:E
D
o u t
C E 1
A d d r e s s
C E 2
W E
D
I N
t
W C
t
A W
t
W R
t
C W
t
A S
t
W P
t
W H Z
t
O W
t
D H
t
D W
H ig h - Z
H ig h - Z
D O N 'T C A R E
U N D E F I N E D
WRITE CYCLE 2
(CE Controlled)
D
o u t
C E 1
A d d r e s
s
C E 2
W E
D
IN
t
W C
t
A W
t
C W
t
W R
t
A S
t
W P
t
D H
t
D W
H ig h - Z
H ig h - Z
D O N 'T C A R E
U N D E F I N E D
NOTES ( WRITE CYCLE ) :
1. A write occurs during the overlap of a low
the lateat transition among
the earliest transition among
measured from the beginning of write to the end of write.
2. tCW is measured from the later of
3. tAS is measured from the address valid to the beginning of write.
4. tWR is measured from the end of write to the address change.
1
CE
, a high CE2 and a low WE. A write begins at
CE
goes low, CE2 going high and WEgoing low. A write end at
1
CE
going high, CE2 going low and WE going high. tWP is
1
1
CE
going low or CE2 going high to the end of write.
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