參數(shù)資料
型號： SY89537LMHTR
廠商： MICREL INC
元件分類： 時鐘產(chǎn)生/分配
英文描述： 756 MHz, OTHER CLOCK GENERATOR, QCC44
封裝： 7 X 7 MM, LEAD FREE, MO-220, MLF-44
文件頁數(shù)： 9/19頁
文件大小： 819K
代理商： SY89537LMHTR
Micrel, Inc.
SY89537L
July 2005
M9999-072105
hbwhelp@micrel.com or (408) 955-1690
17
Output Bank and Frequency Control
There are five independently programmable output
frequency banks, four differential LVPECL output
banks and one differential LVDS output bank with
three output pairs. Each bank has frequency control
SELx and Enx to generate different divider ratios (see
“PECL and LVDS Output and Frequency Select”
Tables). It can be programmed for pass-through,
internal divided VCO clock divide-by- /2, /8 or disable
state. When disabled, the non-inverted output goes to
static LOW and the inverted output goes to static
HIGH.
Output Logic Characteristics
See “Output Termination Recommendations” for
proper termination. When LVPECL single-ended
output is desired, the unused complimentary output
should be terminated. Unused LVPECL output pairs
can be left floating. LVDS output pairs should be
terminated with 100 across the pair. In order to
minimize jitter and skew, unused LVDS output banks
and unused LVDS output pairs should be terminated
with 100 across each pair.
LVPECL Outputs:
Typical voltage swing is 800mV into 50.
Common mode voltage is VCCO–1.3V.
LVDS Outputs:
Typical voltage swing is 325mV into 100.
Common mode voltage is 1.2V.
Output Termination Recommendations
LVPECL
LVPECL has high input impedance, very low output
(open emitter) impedance, and small signal swing
which results in low EMI. LVPECL is ideal for driving
50-and-100-controlled
impedance
transmission
lines. There are several techniques for terminating the
LVPECL output: Parallel Termination Thevenin-
Equivalent, Parallel Termination (3-resistor), and AC-
coupled termination. Unused output pairs may be left
floating. However, single-ended outputs must be
terminated, or balanced.
Figure 12a. Parallel Thevenin-Equivalent
Figure 12b. Parallel Termination
LVDS
LVDS specifies a small swing of 325mV typical, on a
nominal 1.2V common mode above ground. The
common mode voltage has tight limits to permit large
variations in ground between an LVDS driver and
receiver. Also, change in common mode voltage, as a
function of data input, is kept to a minimum, to keep
EMI low.
Figure 13a. LVDS Differential Measurement
Figure 13b. LVDS Common Mode Measurement
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
SY89537LMY 功能描述:時鐘合成器/抖動清除器 3.3V LVPECL/LVDS Clock Synthesizer System (I Temp, Green) RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel
SY89537LMY TR 功能描述:時鐘合成器/抖動清除器 3.3V LVPECL/LVDS Clock Synthesizer System (I Temp, Green) RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel
SY89537LMYTR 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:3.3V Precision LVPECL and LVDS
SY89538L 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:3.3V, Precision LVPECL and LVDS Programmable Multiple Output Bank Clock Synthesizer and Fanout Buffer with Zero Delay
SY89538L_06 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:3.3V, Precision LVPECL and LVDS Programmable Multiple Output Bank Clock Synthesizer and Fanout Buffer with Zero Delay
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