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參數(shù)資料
| 型號： | SY89537LMHTR |
| 廠商： | MICREL INC |
| 元件分類： | 時(shí)鐘產(chǎn)生/分配 |
| 英文描述： | 756 MHz, OTHER CLOCK GENERATOR, QCC44 |
| 封裝： | 7 X 7 MM, LEAD FREE, MO-220, MLF-44 |
| 文件頁數(shù)： | 15/19頁 |
| 文件大小： | 819K |
| 代理商： | SY89537LMHTR |
Micrel, Inc.
SY89537L
July 2005
M9999-072105
hbwhelp@micrel.com or (408) 955-1690
5
Pin Description (continued)
Input/Output
Pin Number
Pin Name
Pin Function
5, 6
RFCK, /RFCK
Reference Clock Differential Input. Input accepts any input, single-ended or differential:
TTL/CMOS, LVPECL, LVDS, HSTL, and SSTL. RFCK requires external termination.
See "Input Interface" section for details.
8, 9
XTAL2, XTAL1
Crystal Input. Directly connect a series resonant crystal across inputs. See “Quartz
Crystal Oscillator Specification” table. Place crystal as close to the input as possible,
keep XTAL and traces away from adjacent noisy traces to minimize noise coupling, and
place the XTAL on the same side as the SY89537L (component side).
12, 13
15, 16
34, 35
37, 38
POUT0, /POUT0
POUT1, /POUT1
POUT2, /POUT2
POUT3, /POUT3
100K LVPECL Output Drivers. Terminate all PECL outputs with 50 to VCCO-2V. Each
output pair has respective output frequency control (PSELx, PENx) pins. See "PECL
Output and Frequency Select Table" for proper coding. For low jitter applications, unused
PECL output pairs should be terminated with pull-down resistors. See "Output
Termination Recommendations" section for termination detail.
25, 26
28, 29
31, 32
LOUT0, /LOUT0
LOUT1, /LOUT1
LOUT2, /LOUT2
Differential LVDS Compatible Output Drivers. Output termination is 100 across the pair.
For low-jitter applications, unused LVDS output pairs should be terminated with 100
across the pair. See “Output Termination Recommendations” section for details.
Reference Input Driver Select Table
RSEL1
RSEL0
Internal Reference
Clock
0
RFCK / 8
0
1
RFCK / 4
1
0
RFCK / 2
1
RFCK / 1
Table 1. Reference Input Divider Select Table
Output and Frequency Select Tables
PSELx
PENx
POUTx
0
Disable Output
0
1
(VCO/4) / 2
1
0
(VCO/4) / 8
1
(VCO/4) / 1
Table 2. PECL Output and Frequency Select Table
LSEL
LEN
LOUTx
0
Disable Output
0
1
(VCO/4) / 2
1
0
(VCO/4) / 8
1
(VCO/4) / 1
Table 3. LVDS Output and Frequency Select Table
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SY89537LMY | 功能描述:時(shí)鐘合成器/抖動清除器 3.3V LVPECL/LVDS Clock Synthesizer System (I Temp, Green) RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| SY89537LMY TR | 功能描述:時(shí)鐘合成器/抖動清除器 3.3V LVPECL/LVDS Clock Synthesizer System (I Temp, Green) RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| SY89537LMYTR | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:3.3V Precision LVPECL and LVDS |
| SY89538L | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:3.3V, Precision LVPECL and LVDS Programmable Multiple Output Bank Clock Synthesizer and Fanout Buffer with Zero Delay |
| SY89538L_06 | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:3.3V, Precision LVPECL and LVDS Programmable Multiple Output Bank Clock Synthesizer and Fanout Buffer with Zero Delay |
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