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參數(shù)資料
| 型號： | SY87813LHG |
| 廠商： | Micrel Inc |
| 文件頁數(shù)： | 9/15頁 |
| 文件大小： | 0K |
| 描述： | IC CLOCK/DATA REC 1.3GBPS 32TQFP |
| 標(biāo)準(zhǔn)包裝： | 250 |
| 系列： | AnyRate® |
| 類型： | 時鐘和數(shù)據(jù)恢復(fù)（CDR），多路復(fù)用器 |
| PLL： | 是 |
| 主要目的： | 以太網(wǎng)，SONET/SDH，ATM 應(yīng)用 |
| 輸入： | PECL |
| 輸出： | PECL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:3 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 1.3Gbps |
| 電源電壓： | 3.15 V ~ 3.45 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-TQFP 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 32-EPAD-TQFP |
| 包裝： | 托盤 |
| 其它名稱： | 576-1586 |
Micrel, Inc.
SY87813L
November 2006
3
M9999-112806-B
hbwhelp@micrel.com or (408) 955-1690
Pin Description
Pin Number
Pin Name
1
REFCLKSEL
REFCLK Select (TTL Input). This input selects the single-ended TTL REFCLK input or the
differential PECL REFCLKP/REFCLKN inputs. REFCLKSEL = HIGH selects PECL inputs.
2
3
RDINP,
RDINN
Serial Data Input. Differential PECL: These built-in line receiver inputs are connected to the
differential receive serial data stream. An internal receive PLL recovers the embedded clock
(RCLK) and data (RDOUT) information. The incoming data rate can be within one of eight
frequency ranges depending upon the state of the FREQSEL pins. See “Frequency
Selection” Table.
4
6
7
FREQSEL1
FREQSEL2
FREQSEL3
Frequency Select. TTL Inputs: These inputs select the output clock frequency range as
shown in the “Frequency Selection” Table.
5
28
29
REFCLK,
REFCLKP,
REFCLKN
Reference Clock. (Input): These inputs are used as the reference for the internal frequency
synthesizer and the “training” frequency for the receiver PLL to keep it centered in the
absence of data coming in on the RDIN inputs. REFCLK is single-ended TTL and REFCLKP
and REFCLKN are differential PECL inputs selected by the REFCLKSEL pin
26
CD
Carrier Detect. PECL Input: This input controls the recovery function of the Receive PLL and
can be driven by the carrier detect output of optical modules or from external transition
detection circuitry. When this input is HIGH, the input data stream (RDIN) is recovered
normally by the Receive PLL. When this input is LOW the data on the inputs RDIN will be
internally forced to a constant LOW, the data outputs RDOUT will remain LOW, the Link Fault
Indicator output LFIN forced LOW and the clock recovery PLL forced to lock onto the clock
frequency generated from REFCLK.
8
NC
No connect.
9
10
PLLSP
PLLSN
Clock Synthesis PLL Loop Filter: External loop filter pins for the clock synthesis PLL.
11
GNDA
Analog Ground.
12, 13
GND
Ground. Ground pin and exposed pad must be connected to the same ground plane.
15
14
PLLRP
PLLRN
Clock Recovery PLL Loop Filter. External loop filter pins for the receiver PLL.
16
TCLKSEL
Clock Select. TTL Input: This input is used to select either the recovered clock of the receiver
PLL (TCLKSEL = HIGH) or the clock of the frequency synthesizer (TCLKSEL = LOW) to the
TCLK outputs.
18
17
TCLKP,
TCLKN
Clock Output (Differential PECL): The PECL 100k outputs represent either the recovered
clock (TCLKSEL = HIGH) used to sample the recovered data (RDOUT) or the transmit clock
of the frequency synthesizer (TCLKSEL = LOW). These outputs must be terminated with 50
to VCC-2V or equivalent. This applies even if these outputs are not used.
19, 22
VCCO
Output Supply Voltage. Bypass with 0.1F//0.01F low ESR capacitors as close to VCC pins
as possible.
(1)
21
20
RCLKP,
RCLKN
Clock Output (Differential PECL): These PECL 100k outputs represent the recovered clock
used to sample the recovered data (RDOUT).
24
23
RDOUTP
RDOUTN
Receive Data Output (Differential PECL): These PECL 100k outputs represent the recovered
data from the input data stream (RDIN). This recovered data is specified against the rising
edge of RCLK. These outputs must be terminated with 50 to VCC-2V or equivalent. This
applies even if these outputs are not used.
32
25
DIVSEL1
DIVSEL2
Divider Select. TTL Inputs: These inputs select the ratio between the output clock frequency
(RCLK/TCLK) and the REFCLK input frequency as shown in the “Reference Frequency
Selection” Table.
Note:
1. VCC, VCCA, VCCO must be the same value.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SY87813LHG TR | 功能描述:計時器和支持產(chǎn)品 3.3V Any-Rate 32-1250 Mbps CDR (PbSn/I Temp/32 Pin EP-TQFP/T+R) RoHS:否 制造商:Micrel 類型:Standard 封裝 / 箱體:SOT-23 內(nèi)部定時器數(shù)量:1 電源電壓-最大:18 V 電源電壓-最小:2.7 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝:Reel |
| SY87813LHGTR | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:3.3V, 28Mbps to 1.3Gbps AnyRate Clock and Data Recovery |
| SY88022ALMG | 功能描述:激光驅(qū)動器 10Gbps FP/DFB LDD w/ Bias RoHS:否 制造商:Micrel 數(shù)據(jù)速率:4.25 Gbps 工作電源電壓:3 V to 3.6 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-16 封裝:Tube |
| SY88022ALMG TR | 功能描述:激光驅(qū)動器 10Gbps FP/DFB LDD w/ Bias RoHS:否 制造商:Micrel 數(shù)據(jù)速率:4.25 Gbps 工作電源電壓:3 V to 3.6 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-16 封裝:Tube |
| SY88022L | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:11.3Gbps Laser Diode Driver |
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