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參數(shù)資料
| 型號： | SY87739LHY TR |
| 廠商： | Micrel Inc |
| 文件頁數(shù)： | 17/17頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC SYNTHESIZER FRACTION N 32TQFP |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 系列： | AnyClock® |
| 類型： | 分?jǐn)?shù)合成器 |
| PLL： | 是 |
| 主要目的： | 以太網(wǎng)，光纖通道，SONET/SDH/ATM |
| 輸入： | PECL |
| 輸出： | PECL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:1 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 729MHz |
| 電源電壓： | 3.15 V ~ 3.45 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-TQFP 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 32-EPAD-TQFP |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | SY87739LHYTR SY87739LHYTR-ND |
Micrel, Inc.
SY87739L
June 2011
9
M9999-061511
hbwhelp@micrel.com
DivSel3
DivSel2
DivSel1
DivSel0
P
0
17
0
1
18
0
1
0
19
0
1
20
0
1
0
21
0
1
0
1
22
0
1
0
23
0
1
24
1
0
25
1
0
1
26
1
0
1
0
27
1
0
1
28
1
0
29
1
0
1
30
1
0
31
1
32
or (408) 955-1690
Table 1. DivSel Divider Setting
Fractional-N Control
This circuit controls the P/P–1 divider, selecting the
appropriate divide ratio, either P or P–1, in the correct
pattern.
As explained in the example of Figure 2 above,
controlling the P/P–1 divider amounts to generating a
repeating binary bit stream. In that example, a “1”
represents dividing by 4, and a “0” represents dividing by
3. The full cycle, “101”, says to divide by 4 twice, and to
divide by 3 once.
In the general case, the pattern “101” need not change
based on the P divider value. To multiply by 14/3 instead
of 11/3, for example, the same “101” pattern would be
used, but we would alternate dividing by 5 and 4, instead
of dividing by 4 and 3. The P value, in effect, represents
the integer part of the multiplication factor.
The repeating binary bit pattern really depends only on
the number of times to divide by P, and the number of
times to divide by P–1. We label the number of times to
divide by P as QP, and the number of times to divide by
P–1 as QP–1. The fractional-N synthesizer generates its
output frequency as per this formula:
fFNOUT =
+
1
P
1
P
Q
P
× f
REF
In Figure 2, we multiply by 11/3, or 41/3. Matching
against the formula, P = 4, QP–1 = 1, and QP =2.
The SY87739L accepts QP and QP–1 values from its
MicroWire interface, where they exist as the 5-bit
values “qp” and “qpm1.” Both values are unsigned binary
numbers. QP and QP-1 are both constrained to be 31 or
less, and their sum is also constrained to be 31 or less.
That means that the denominator in the above formula
must be 31 or less.
As would be expected from the formula, setting QP to
zero causes frequency multiplication exactly by P–1.
Setting QP–1 to zero causes frequency multiplication
exactly by P. The SY87739L behavior is undefined if
both QP and QP–1 are both set to zero.
In the general case, the length of the repeating binary bit
pattern is QP + QP–1. It consists of QP “1”, and QP–1 “0.”
The SY87739L accomplishes this by implementing
Bresenham’s algorithm in hardware. To see how this
works, we need a more complicated example. Let’s say
we need to multiply by 110/23, or 5 – 5/23. In this
example, P = 5, QP–1 = 5, and QP = 18. The nave
approach would generate a bit pattern of:
11111 11111 11111 11100 000
The spaces between groups of five digits are added for
readability only. This pattern is 23 bits long, with QP (that
is, 18) “1” and QP–1 (that is, 5) “0”, so it will multiply
correctly, but it doesn’t match P/P–1 divider edges to
input edges in the best way possible.
In fact, the best pattern, in terms of minimizing distance
between divider and reference input edges, is:
11110 11110 1110 11110 1110
Table 2 shows how Bresenham’s algorithm works. The
first column is an accumulator. It starts at zero, but
otherwise takes the result from the fourth column of the
previous row. The second column is the value to add to
the accumulator at each step. In the general case, this is
always QP–1. The third column forms the sum. The fourth
column takes the sum modulo (QP + QP–1).
The last column is “0” whenever the modulo changes the
sum. Note that the Table has 23 rows, before the sum is
zero, and the entire algorithm repeats itself.
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