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參數(shù)資料
| 型號： | SY87739LHY TR |
| 廠商： | Micrel Inc |
| 文件頁數(shù)： | 16/17頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC SYNTHESIZER FRACTION N 32TQFP |
| 標準包裝： | 1,000 |
| 系列： | AnyClock® |
| 類型： | 分數(shù)合成器 |
| PLL： | 是 |
| 主要目的： | 以太網(wǎng)，光纖通道，SONET/SDH/ATM |
| 輸入： | PECL |
| 輸出： | PECL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:1 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 729MHz |
| 電源電壓： | 3.15 V ~ 3.45 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-TQFP 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 32-EPAD-TQFP |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | SY87739LHYTR SY87739LHYTR-ND |
Micrel, Inc.
SY87739L
June 2011
8
M9999-061511
hbwhelp@micrel.com
Whereas P sets the integer part of the multiplication
factor from input to output frequency, the control circuit
determines the fractional part. By mixing the output of
the P and P–1 dividers correctly, the control circuit can
fashion any output frequency from P–1 times the input to
P times the input, as long as that ratio can be expressed
as a ratio of integers.
Figure 2. 11/3 Example
Figure 2 shows an example generating an output
frequency 3 2/3 times the input frequency. Since the
output frequency is between 3 and 4 times the input, P is
set to 4. We need to select the P divider twice, and
select the P–1 divider once. Multiplying by 4 two times
out of three, and multiplying by 3 one time out of three,
averages to a multiplication of 32/3.
The top waveform is the reference input. The bottom
waveform is the multiplied output. The waveform in the
middle shows those edges from the output that most
closely matches a corresponding reference waveform
edge.
The control circuit must generate a repeating pattern to
the mux of something like “101”, so that the P divider is
selected twice, and the P–1 divider is selected once,
every three reference edges.
Fractional-N Phase-Frequency Detector
This circuit, besides generating “pump up” and “pump
down” signals, also generates delta phase signals for
use by the lock detect circuit.
This detector circuit also accepts a gating signal from the
fractional-N control block. When gated, the phase
detector generates neither pump up nor pump down
pulses.
or (408) 955-1690
Fractional-N Charge Pump
This circuit converts the “pump up” and “pump down”
signals from the phase-frequency detector into current
pulses. An external loop filter integrates these current
pulses into a control voltage.
Charge pump current is selectable. This modifies loop
gain as follows:
During acquisition of the reference, the charge
pump current is fixed at 20A. Once the
acquisition sequencer has completed center
frequency trimming, then it changes the current
of this charge pump to 50A.
Fractional-N VCO
This circuit converts the voltage integrated by the
external loop filter into a digital clock stream. The
frequency of this clock varies based on this control
voltage. This VCO has a coarse and a fine input, with a
combined range of 540MHz to 729MHz. The coarse
input trims the VCO, as described below, so that its
center frequency rests near the target frequency to
generate. The fine adjustment forms part of the closed
loop. VCO gain is nominally 200MHz per volt.
Fractional-N P/P-1 Divider
This is the main divider for the fractional-N loop. The
logical value of the output of the control block (Figure 1)
defines whether the divider divides by P (values shown
in Table 1) or by P–1. The expression for the fractional
division becomes:
Fractional Division =
()
+
P
1
P
1
P
Q
P
Where QP is the number of reference clock periods
during which the divider must divide by P and QP-1 is the
number of reference clock periods during which the
divider must divide by P–1.
Care should be exercised when selecting the value of P
(Table 1) so that the voltage-controlled oscillator (VCO)
of the fractional-N PLL is not driven out of range. The
following conditions must be met:
fVCO(MIN) < fREF × Fractional Division < fVCO(MAX)
or
fVCO(MIN) < fREF ×
(
)
+
P
1
P
1
P
Q
P
< f
VCO(MAX)
where:
fVCO(MIN) = 540MHz
fVCO(MAX) = 729MHz
fREF = Frequency of the reference clock
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