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參數(shù)資料
| 型號(hào)： | SY87721LHG |
| 廠商： | Micrel Inc |
| 文件頁(yè)數(shù)： | 13/16頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK/DATA RECOVERY 64-TQFP |
| 標(biāo)準(zhǔn)包裝： | 160 |
| 系列： | AnyRate® |
| 類型： | 時(shí)鐘和數(shù)據(jù)恢復(fù)（CDR），多路復(fù)用器 |
| PLL： | 是 |
| 主要目的： | 以太網(wǎng)，SONET/SDH，ATM 應(yīng)用 |
| 輸入： | PECL |
| 輸出： | CML，PECL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:6 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 2.7GHz |
| 電源電壓： | 3.15 V ~ 3.45 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-TQFP 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 64-EP-TQFP |
| 包裝： | 托盤 |
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SY87721L
6
Micrel, Inc.
M9999-012508
hbwhelp@micrel.com or (408) 955-1690
OUTPUTS
BRD
± [Buffered Recovered Data] – Differential CML Output
The signal is either a buffered RDIN
± or RDOUTC±,
depending on the state of the BRDMX input. This allows a
user to selectively bypass the CDR or not, as warranted by
architecture. This CML output has a voltage swing of 400mV
loaded.
LFIN [Link Fault Indicate] – O.C. TTL Output
This output indicates the status of the input data stream
RDIN. Active HIGH indicates that the internal clock recovery
PLL has locked onto the incoming data stream. LFIN will go
HIGH if CD is HIGH and RDIN is within the frequency range
of the Receive PLL (as per ALRSEL). LFIN is an
asynchronous output.
RDOUTE
± [Receive Data Out] – Differential PECL Output
These ECL 100K outputs (+3.3V referenced) represent
the recovered data from the input data stream (RDIN). It is
specified on the rising edge of RCLK.
RDOUTC
± [Receive Data Out] – Differential CML Output
This is the CML version of RDOUTE
±.
RCLKE
± [Receive Clock Out] – Differential PECL Output
These ECL 100K outputs (+3.3V referenced) represent
the recovered clock used to sample the recovered data
(RDOUT).
RCLKC
± [Receive Clock Out] – Differential CML Output
This is the CML version of RCLKE
±.
TCLKE
± [Transmit Clock Out] – Differential PECL Output
These ECL 100K outputs (+3.3V referenced) represent
either the recovered clock (CLKSEL = HIGH) used to sample
the recovered data (RDOUT) or the transmit clock of the
frequency synthesizer (CLKSEL = LOW).
TCLKC
± [Transmit Clock Out] – Differential CML Output
This is the CML version of TCLKE
±.
PLLSN+, PLLSN– [Clock Synthesis Loop Filter]
External loop filter pins for the clock synthesis narrow
band PLL.
PLLSW+, PLLSW– [Clock Synthesis Loop Filter]
External loop filter pins for the clock synthesis wide band
PLL.
PLLRN+, PLLRN– [Clock Recovery Loop Filter]
External loop filter pins for the clock recovery narrow
band PLL.
PLLRW+, PLLRW– [Clock Recovery Loop Filter]
External loop filter pins for the clock recovery wide band
PLL.
OTHERS
VCC
Supply Voltage
VCCO
Output Supply Voltage
VCCA
Analog Supply Voltage
GND
Ground
GNDA
Analog Ground
NC
These pins are for factory test, and are to be
left unconnected during normal use.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SY87721LHGTR | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:3.3V 28Mbps-2.7Gbps ANYRATE CLOCK AND DATA RECOVERY WITH INTEGRATED CLOCK MULTIPLIER UNIT |
| SY87721LHI | 功能描述:IC CLOCK/DATA RECOVERY 64-TQFP RoHS:否 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 專用 系列:AnyRate® 標(biāo)準(zhǔn)包裝:1,500 系列:- 類型:時(shí)鐘緩沖器/驅(qū)動(dòng)器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱:93786AFT |
| SY87721LHITR | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:CLOCK AND DATA RECOVERY WITH INTEGRATED CLOCK MULTIPLIER UNIT |
| SY87721LHY | 功能描述:計(jì)時(shí)器和支持產(chǎn)品 3.2V Any-Rate CDR 28 Mbps-2.7 Gbps (I Temp, Lead Free/64 TQFP) RoHS:否 制造商:Micrel 類型:Standard 封裝 / 箱體:SOT-23 內(nèi)部定時(shí)器數(shù)量:1 電源電壓-最大:18 V 電源電壓-最小:2.7 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝:Reel |
| SY87721LHY TR | 功能描述:計(jì)時(shí)器和支持產(chǎn)品 3.2V Any-Rate CDR 28 Mbps-2.7 Gbps (I Temp, Lead Free/64 TQFP) RoHS:否 制造商:Micrel 類型:Standard 封裝 / 箱體:SOT-23 內(nèi)部定時(shí)器數(shù)量:1 電源電壓-最大:18 V 電源電壓-最小:2.7 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝:Reel |
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