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參數(shù)資料
| 型號： | SY87700ALHG TR |
| 廠商： | Micrel Inc |
| 文件頁數(shù)： | 10/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK/DATA RECOVERY 32-TQFP |
| 標準包裝： | 1,000 |
| 系列： | AnyRate® |
| 類型： | 時鐘和數(shù)據(jù)恢復(fù)（CDR），多路復(fù)用器 |
| PLL： | 是 |
| 主要目的： | 以太網(wǎng)，SONET/SDH，ATM 應(yīng)用 |
| 輸入： | PECL |
| 輸出： | PECL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:3 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 208Mbps |
| 電源電壓： | 3.15 V ~ 3.45 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-TQFP 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 32-EPAD-TQFP |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | SY87700ALHGTR SY87700ALHGTR-ND |
Micrel, Inc.
SY87700AL
August 2009
3
M9999-082009-D
hbwhelp@micrel.com or (408) 955-1690
Pin Description
Inputs
Pin Number
(28-SOIC)
Pin Number
(32-TQFP)
Pin Name
4,
5
2,
3
RDINP,
RDINN
Serial Data Input. Differential PECL: These built-in line receiver inputs are
connected to the differential receive serial data stream. An internal receive
PLL recovers the embedded clock (RCLK) and data (RDOUT) information.
The incoming data rate can be within one of eight frequency ranges
depending on the state of the FREQSEL pins. See “Frequency Selection”
Table.
7
5
REFCLK
Reference Clock. TTL Input: This input is used as the reference for the
internal frequency synthesizer and the “training” frequency for the receiver
PLL to keep it centered in the absence of data coming in on the RDIN inputs
27
26
CD
Carrier Detect. PECL Input: This input controls the recovery function of the
Receive PLL and can be driven by the carrier detect output of optical
modules or from external transition detection circuitry. When this input is
HIGH the input data stream (RDIN) is recovered normally by the Receive
PLL. When this input is LOW the data on the inputs RDIN will be internally
forced to a constant LOW, the data outputs RDOUT will remain LOW, the
Link Fault Indicator output LFIN forced LOW and the clock recovery PLL
forced to lock onto the clock frequency generated from REFCLK.
6
8
9
4
6
7
FREQSEL1
FREQSEL2
FREQSEL3
Frequency Select. TTL Inputs: These inputs select the output clock frequency
range as shown in the “Frequency Selection” Table.
3
26
32
25
DIVSEL1
DIVSEL2
Divider Select. TTL Inputs: These inputs select the ratio between the output
clock frequency (RCLK/TCLK) and the REFCLK input frequency as shown in
the “Reference Frequency Selection” Table.
17
16
CLKSEL
Clock Select. TTL Input: This input is used to select either the recovered
clock of the receiver PLL (CLKSEL = HIGH) or the clock of the frequency
synthesizer (CLKSEL = LOW) to the TCLK outputs.
Outputs
2
31
LFIN
Link Fault Indicator. TTL Output: This output indicates the status of the input
data stream RDIN. Active HIGH signal is indicating when the internal clock
recovery PLL has locked onto the incoming data stream. LFIN will go HIGH if
CD is HIGH and RDIN is within the frequency range of the Receive PLL
(1000ppm). LFIN is an asynchronous output.
25
24
23
RDOUTP
RDOUTN
Receive Data Output. Differential PECL: These ECL 100k outputs represent
the recovered data from the input data stream (RDIN). This recovered data is
specified against the rising edge of RCLK.
22, 21
21, 20
RCLKP,
RCLKN
Clock Output. Differential PECL: These ECL 100k outputs represent the
recovered clock used to sample the recovered data (RDOUT).
19, 18
18, 17
TCLKP,
TCLKN
Clock Output. Differential PECL: These ECL 100k outputs represent either
the recovered clock (CLKSEL = HIGH) used to sample the recovered data
(RDOUT) or the transmit clock of the frequency synthesizer (CLKSEL =
LOW).
11, 12
9, 10
PLLSP,
PLLSN
Clock Synthesis PLL Loop Filter: External loop filter pins for the clock
synthesis PLL.
16, 15
15, 14
PLLRP,
PLLRN
Clock Recovery PLL Loop Filter: External loop filter pins for the receiver PLL.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SY87700ALZG | 功能描述:計時器和支持產(chǎn)品 3.3V 32Mbps-175Mbps CDR (I Temp, Green/28 pin SOIC/bulk) RoHS:否 制造商:Micrel 類型:Standard 封裝 / 箱體:SOT-23 內(nèi)部定時器數(shù)量:1 電源電壓-最大:18 V 電源電壓-最小:2.7 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝:Reel |
| SY87700ALZG TR | 功能描述:計時器和支持產(chǎn)品 3.3V 32Mbps-175Mbps CDR (I Temp, Green/28 pin SOIC/T+R) RoHS:否 制造商:Micrel 類型:Standard 封裝 / 箱體:SOT-23 內(nèi)部定時器數(shù)量:1 電源電壓-最大:18 V 電源電壓-最小:2.7 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝:Reel |
| SY87700L | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:3.3V 32-175Mbps AnyRate CLOCK AND DATA RECOVERY |
| SY87700L_06 | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:3.3V 32-175Mbps AnyRate CLOCK AND DATA RECOVERY |
| SY87700LHG | 功能描述:計時器和支持產(chǎn)品 3.3V 32Mbps-175Mbps CDR (I Temp, Green/32 pin TQFP/bulk) RoHS:否 制造商:Micrel 類型:Standard 封裝 / 箱體:SOT-23 內(nèi)部定時器數(shù)量:1 電源電壓-最大:18 V 電源電壓-最小:2.7 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝:Reel |
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