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參數(shù)資料
| 型號： | SY100EP196VTI TR |
| 廠商： | Micrel Inc |
| 文件頁數(shù)： | 7/18頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DELAY LINE 1024TAP 32-TQFP |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 系列： | 100EP, ECL Pro® |
| 標(biāo)片/步級數(shù)： | 1024 |
| 功能： | 可編程 |
| 延遲到第一抽頭： | 2.05ns |
| 接頭增量： | 10ps |
| 可用的總延遲： | 2.05ns ~ 12.2ns |
| 獨(dú)立延遲數(shù)： | 1 |
| 電源電壓： | 3 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-TQFP |
| 供應(yīng)商設(shè)備封裝： | 32-TQFP |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | SY100EP196VTITR SY100EP196VTITR-ND |
15
ECL Pro
SY100EP196V
Micrel, Inc.
M9999-072706
hbwhelp@micrel.com or (408) 955-1690
For best performance, use good high frequency layout
techniques, filter VCC supplies, and keep ground connections
short. Use multiple vias where possible. Also, use controlled
impedance transmission lines to interface with the
SY100EP196V data inputs and outputs.
VBB Supply
The VBB pin is an internally generated supply, and is
available for use only by the SY100EP196V. When unused,
this pin should be left unconnected. The two common uses
for VBB are to handle a single-ended PECL input, and to re-
bias inputs for AC-coupling applications.
If IN, /IN is driven by a single-ended output, VBB is used
to bias the unused input. Please refer to Figures 9. The
PECL signal driving SY100EP196V may optionally be
inverted in this case.
When the signal is AC-coupled, VBB is used, as shown
in Figure 10, to re-bias IN, /IN. This ensures that
SY100EP196V inputs are within its acceptable common
mode range.
In all cases, VBB current sinking or sourcing must be
limited to 0.5mA or less.
APPLICATIONS INFORMATION
Setting D Input Logic Thresholds
As explained earlier, in all designs where the
SY100EP196V VEE supply is at zero volts, the D inputs
may accommodate CMOS and TTL level signals, as well as
PECL or LVPECL. Figures 9 show how to connect VCF and
VEF for all possible cases.
Cascading
Two or more SY100EP196V may be cascaded, in order
to extend the range of delays permitted. Each additional
SY100EP196V adds about 2200ps to the minimum delay,
and adds another 10240ps to the delay range.
Internal cascade circuitry has been included in the
SY100EP196V. Using this internal circuitry, SY100EP196V
may be cascaded without any external gating.
Examples of cascading 2, 3, or 4 SY100EP196V appear
in Figures 10. Table 7 lists the nominal delay for all the
cases that appear in Figures 10.
IN
/IN
Q
/Q
IN
/IN
Q
FTUNE
/Q
D[9:0]
SY100EP196V
#2
#1
SETMIN
SETMAX
/CASCADE
CASCADE
D[10]
C[9:0]
C[10]
Control Word (11bits)
DAC
Figure 10a. Cascading Two SY100EP196V
IN
/IN
Q
/Q
IN
/IN
Q
/Q
SY100EP196V
#3
DAC
#2
SETMIN
SETMAX
SETMIN
SETMAX
/CASCADE
CASCADE
D[10]
C[11]
IN
/IN
Q
FTUNE
/Q
D[9:0]
SY100EP196V
#1
/CASCADE
CASCADE
D[10]
C[9:0]
C[10]
Control Word (12bits)
Figure 10b. Cascading Three SY100EP196V
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