參數(shù)資料
型號: SY100E193JC
廠商: Micrel Inc
文件頁數(shù): 1/5頁
文件大小: 0K
描述: IC PARITY GENERATOR 8BIT 28PLCC
標(biāo)準(zhǔn)包裝: 38
系列: 100E
邏輯類型: 奇偶發(fā)生器
電路數(shù): 8 位
電源電壓: 4.2 V ~ 5.5 V
工作溫度: 0°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 28-LCC(J 形引線)
供應(yīng)商設(shè)備封裝: 28-PLCC
1
SY10E193
SY100E193
Micrel, Inc.
M9999-032006
hbwhelp@micrel.com or (408) 955-1690
Pin
Function
B0–B7
Check Bit Inputs
BPAR
Check Bit Parity Input
EV/OD
Even/Odd Parity Select
EN
Parity Enable
HOLD
Syndrome Hold Input
S-IN
Syndrome Bit Input
SHIFT
Syndrome Bit Shift
CLK
Clock Input
P1–P5
Parity Output
PGEN
Parity Generate Output
PARERR/PARERR
Parity Error Output
VCCO
VCC to Output
s Hamming code generation
s Extended 100E VEE range of –4.2V to –5.5V
s 8-bit wide
s Expandable for more width
s Provides parity register
s Fully compatible with industry standard 10KH,
100K ECL levels
s Internal75K
input pulldown resistors
s Fully compatible with Motorola MC10E/100E193
s Available in 28-pin PLCC package
FEATURES
The SY10/100E193 are error detection and correction
(EDAC) circuits designed for use in new, high- performance
ECL systems. The E193 generates hamming parity codes
on an 8-bit word as shown in the block diagram. The P5
output gives the parity of the whole word. PGEN provides
word parity after Odd/Even parity control and gating with
the BPAR input. PGEN also feeds into a 1-bit shiftable
register for use as part of a scan ring.
The combinatorial part of the device generates the same
code pattern as the Motorola MC10193.
Used in conjunction with 12-bit parity generators, such
as the E160, a SECDED (single error correction, double
error detection) error system can be designed for a multiple
of an 8-bit word.
DESCRIPTION
ERROR DETECTION/
CORRECTION CIRCUIT
PIN NAMES
SY10E193
SY100E193
Rev.: F
Amendment: /0
Issue Date:
March 2006
相關(guān)PDF資料
PDF描述
SY100E160JC IC PARITY GEN/CHKER 12BIT 28PLCC
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