參數(shù)資料
型號(hào)： SX20AC75
廠商： Electronic Theatre Controls, Inc.
英文描述： Configurable Communications Controllers with EE/Flash Program Memory, In-System Programming Capability and On-Chip Debug
中文描述： 配置通信控制器與電子工程/閃存程序存儲(chǔ)器，在系統(tǒng)編程能力和片上調(diào)試
文件頁(yè)數(shù)： 7/52頁(yè)
文件大?。?/td> 688K
代理商： SX20AC75
2000 Scenix Semiconductor, Inc. All rights reserved.
- 7 -
www.scenix.com
SX18AC/SX20AC/SX28AC/SX18AC75/SX20AC75/SX28AC75
3.0
The device contains a 4-bit I/O port (Port A) and two 8-bit
I/O ports (Port B, Port C). Port A provides symmetrical
drive capability. Each port has three associated 8-bit reg-
isters (Direction, Data, TTL/CMOS Select, and Pull-Up
Enable) to configure each port pin as Hi-Z input or output,
to select TTL or CMOS voltage levels, and to enable/dis-
able the weak pull-up resistor. The upper four bits of the
registers associated with Port A are not used. The least
significant bit of the registers corresponds to the least
significant port pin. To access these registers, an appro-
priate value must be written into the MODE register.
Upon power-up, all bits in these registers are initialized to
“1”.
PORT DESCRIPTIONS
The associated registers allow for each port bit to be indi-
vidually configured under software control as shown
below:
Table 3-1. Port Configuration
3.1
The three ports are memory-mapped into the data mem-
ory address space. To the CPU, the three ports are avail-
able as the RA, RB, and RC file registers at data memory
addresses 05h, 06h, and 07h, respectively.
Reading and Writing the Ports
Writing to a port data register sets the voltage levels of
the corresponding port pins that have been configured to
operate as outputs. Reading from a register reads the
voltage levels of the corresponding port pins that have
been configured as inputs.
Data Direction
Registers:
RA, RB, RC
TTL/CMOS
Select Registers:
LVL_A, LVL_B,
LVL_C
Pullup Enable
Registers:
PLP_A, PLP_B,
PLP_C
0
1
0
1
0
1
Output
Hi-Z
Input
CMOS
TTL
Enable
Disable
Figure 3-1. Port A Configuration
MODE
RA
RA Data
LVL_A
0 = Output
1 = Hi-Z Input
WR
WR
0 = CMOS
1 = TTL
RD
TTL Buffer
CMOS Buffer
V
dd
Pullup
Port A PIN
I
M
U
X
M
M
M
WR
Direction
PLP_A
0 = Pullup Enable
1 = Pullup Disable
Port A INPUT
WR
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