參數(shù)資料
型號: SUM40N02-09P
廠商: Vishay Intertechnology,Inc.
英文描述: N-Channel 20-V (D-S), 175∑C MOSFET
中文描述: N溝道20五(副),175ΣCMOSFET的
文件頁數(shù): 2/3頁
文件大小: 175K
代理商: SUM40N02-09P
SPICE Device Model SUM40N02-09P
Vishay Siliconix
www.vishay.com
2
Document Number: 72198
08-Jun-04
SPECIFICATIONS (T
J
= 25
°
C UNLESS OTHERWISE NOTED)
Parameter
Symbol
Test Conditions
Simulated
Data
Measured
Data
Unit
Static
Gate Threshold Voltage
V
GS(th)
V
DS
= V
GS
, I
D
= 250
μ
A
1.7
V
On-State Drain Current
a
I
D(on)
V
DS
= 5 V, V
GS
= 10 V
438
A
V
GS
= 10 V, I
D
= 20 A
0.0078
0.008
V
GS
= 10 V, I
D
= 20 A, T
J
= 125
°
C
0.010
Drain-Source On-State Resistance
a
r
DS(on)
V
GS
= 4.5 V, I
D
= 20 A
0.0136
0.0135
Forward Voltage
a
Dynamic
b
V
SD
I
F
= 40 A, V
GS
= 0 V
0.91
1.1
V
Input Capacitance
C
iss
1212
1300
Output Capacitance
C
oss
470
470
Reverse Transfer Capacitance
C
rss
V
GS
= 0 V, V
DS
= 10 V, f = 1 MHz
237
275
pF
Total Gate Charge
c
Q
g
10.6
10.5
Gate-Source Charge
c
Q
gs
4.2
4.2
Gate-Drain Charge
c
Q
gd
V
DS
= 10 V, V
GS
= 4.5 V, I
D
= 40 A
4
4
nC
Turn-On Delay Time
c
t
d(on)
9
8
Rise Time
c
t
r
9
10
Turn-Off Delay Time
c
t
d(off)
32
25
Fall Time
c
t
f
V
DD
= 10 V, R
L
= 0.25
I
D
40 A, V
GEN
= 10 V, R
G
= 2.5
10
12
Source-Drain Reverse Recovery Time
t
rr
I
F
= 40 A, di/dt = 100 A/
μ
s
31
35
ns
Notes
a.
b.
c.
Pulse test; pulse width
300
μ
s, duty cycle
2%.
Guaranteed by design, not subject to production testing.
Independent of operating temperature.
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