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參數(shù)資料
| 型號： | STV9432TAP |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 100MHz OSD FOR MONITOR INCLUDING BEAM CURRENTS, VIDEO TIMING ANALYZER AND PWMs |
| 中文描述： | 100MHz的OSD用于顯示器包括離子束電流，視頻定時(shí)分析儀和PWM |
| 文件頁數(shù)： | 14/18頁 |
| 文件大?。?/td> | 186K |
| 代理商： | STV9432TAP |
STV9432
14/18
Capture Process Time Constant
(reset value: 24H)
4036
LEN
Initial Pixel Period
(reset value: 06H)
4037
PP7
8.4 - OSD TIMINGS
The number of pixel periods is given by the LINE
DURATION register and is equal to:
[LD[6:1] x 2 + 1 ] x 12.
(LD[6:1]: value of the LINE DURATION register).
This value is used to define the horizontal size of
the characters.
The horizontal left margin is given by the HORI-
ZONTAL DELAY register and is equal to:
(DD[7:0] -6) x 6 + 54
(DD[7:0]: value of the DISPLAY DELAY register).
This value is used to define the horizontal position
of the characters on the screen. Due to internal
logic, minimum horizontal delay is fixed at 4.5
characters (54 pixel) when DD is even and inferior
or equal to 6, and it is fixed at 5 characters (60
pixel) when DD is odd and inferior or equal to 7.
8.5 - PLL
The PLL function of the STV9432 provides the
internal pixel clock locked on the horizontal syn-
chro signal and used by the display processor to
generate the R, G, B and fast blanking signals. It
is made of 2 PLLs. The first PLL which is analog
(see
Figure 6
) provides a high frequency that is 40
times the internal oscillator frequency, or 320MHz.
This high frequency clock is used by the Display
controller.
The 320MHz frequency is then divided by three.
The resulting 106.7MHz clock is used by the
Video timings analysis block.
The second PLL, fully digital (see
Figure 7
), pro-
vides a pixel frequency locked on the horizontal
synchro signal. The ratio between the frequencies
of these 2 signals is:
M = 12 x (LD[6:1] x 2 + 1) where LD[6:1] is the
value of the LINE DURATION register.
Figure 6. Analog PLL
Figure 7. Digital PLL
8.5.1 - Programming of the PLL Registers
Initial Pixel Period
(@4037)
This register allows to increase the speed of the
PLL convergence when the horizontal frequency
changes (new graphic standard).
The relationship between PP[7:0], LD[6:1], f
HSYNC
and f
OSC
is:
PP[7:] = round
(
AF2
AF1
AF0
-
BF2
BF1
BF0
LEN
:
Lock enable
0 = R,G,B, FBLK are always enabled,
1 = R,G,B,, FBLK are enabled only when PLL is locked.
Phase constant during the capture process.
Frequency constant during the capture process.
AF[2:0]
BF[2:0]
:
:
PP6
PP5
PP4
PP3
PP2
PP1
PP0
PP[7:0]
:
Value to initialize the pixel period of the PLL.
VCO
40
FILTER
N f
OSC
f
OSC
%D
%M
ALGO
M f
H-SYNC
f
H-SYNC
err(n)
D(n)
40 f
OSC
40
.
f
OSC
6
.
(2
.
LD + 1)
.
f
HSYNC
)
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