
PIN DESCRIPTION
Pin
1
Symbol
V
DD
A11, A12, A10
Function
+5V
Chapter address
Description
Positive supply voltage
Address selectionoutputs for 1 of 8 external static
RAM chapters each of 1 kBytes.
Active-low external static RAM output enable control
signal.
Active-low external static RAM write enable control
signal. It supports write-cycles interleaved with
read-cycles.
An A.C. coupled teletext data input supplied by the
SAA5231 chip is latched to V
SS
between 4 and 8
μ
s
after each TV line.
A 6.9375MHz clock signal, supplied by the SAA5231
chip, is internally A.C. coupled, clamped and
buffered.
High for even numbered and low for odd-numbered
frames. The value is valid 2
μ
s before the end of
lines 311and 624.
The 6MHz clock signal,supplied by the SAA5231
chip is internallyA.C. coupled, clamped and buffered.
Active high VCS input.
2,3,40 *
4 *
OE
Output enable
5 *
WE
Write enable
6
TTD
Teletext data input
7
TTC
Teletext clock input
8
ODD/EVEN
Interlaced mode state output
9
F6
Character display clock signal
10
VCS
Video composite
synchronization input signal
Sandcastle
11
SAND
Three level output pulse to the SAA5231 device.
Phase lock, blanking signal, and color burst
components are contained in this signal.
Scan composite input signal (SCS) for the display
synchronization or Text composite sync. (TCS)
output signal to the SAA5231. Both signals are
active low.
Character and background colors active-high
open-drain outputs.
Open-drain active-low output supporting optimal
display of characters in ”mixed mode”operation.
Open-drain active high output for TV-image blanking
in normal and mixed-mode operation.
Open-drain active-high output with foreground
information. Can be used for printercommand.
Microprocessor clock input via serial bus.
Open-drain microprocessor serial data input/output
via serial bus.
Ground.
Eight tri-state input/output for data read/write from/to
an external static RAM.
Tenaddresses output pins for accessing to
individual Bytes of a 1 kByte chapter stored in an
external Static RAM.
12
TCS/SCS
Input / output composite
synchronization signal
13,14,15
R G B
Red, green, blue
16
COR
Contrast reduction
17
BLAN
Blanking signal output
18
Y
Foreground output
19
20
SCL
SDA
Serial clock
Serial data input / output
21
V
SS
D0-D7
0 Volt
22-29 *
Parallel data input / output
30-39 *
A0-A9
Address signals
5
* Pins only activated when 8KBytes of external memory are addressed, otherwise pins OE and WE remain high, andothers remain low.
STV5345 - STV5345/H- STV5345/T
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