參數(shù)資料
型號(hào)： STV0684
廠商： 意法半導(dǎo)體
英文描述： Digital Camera Processor
中文描述： 數(shù)碼相機(jī)處理器
文件頁(yè)數(shù)： 37/49頁(yè)
文件大小： 487K
代理商： STV0684
37/49
STV0684
Electrical Characteristics
4.5.8
AC characteristics for NAND flash operation
Note: 1 All parameters relating to the CE_n signal are omitted as it is not enabled/disabled during execution
of any NAND flash operation i.e. it is permanently tied low.
2 All timings are worst case
3 Conforms to both Samsung and Toshiba specifications as outlined in datasheets.
4 The NAND flash timings detailed here are guaranteed by design.
5 The loading factor used for the characterization is equivalent to 40pF
4.5.9
Compact flash timing
There are two types of bus cycles and timing sequences that occur in the PCMCIA type interface,
direct mapped I/O transfer and memory access. The STV0684 will only support the memory
mapped mode.
Table 12: AC characteristics for NAND flash operation
Symbol
Parameter
Min
Typical
Max
Units
t
CLS
CLE Set-up time
61.4
62.4
ns
t
CLH
CLE Hold time
83.2
ns
t
WP
WE-n Pulse Width
83.2
ns
t
ALS
ALE Set-up time
82.6
83.2
ns
t
ALH
ALE Hold time
82.4
83.2
ns
t
DS
Data Set-up time
82.6
83.2
ns
t
DH
Data Hold time
61.8
62.4
ns
t
WC
Write Cycle time
145.1
145.6
ns
t
WH
WE_n High Hold time
61.9
62.4
ns
t
RR
Ready to RE_n Low
81
83
ns
t
RP
RE_n Pulse Width
83.2
ns
t
RC
Read Cycle time
187.2
ns
t
REA
RE_n Access time
35
43.2
ns
t
REH
RE_n High Hold time
103.5
104
ns
t
WHR
WE_n High to RE_n Low
124.2
124.8
ns
t
R
Data Transfer from Cell to Register
25.015
μs
t
WB
WE_n High to Busy
41.6
215.3
ns
t
RST
Device Resetting (Read)
5.015
μs
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