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參數(shù)資料
| 型號： | STV0056AF |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | Satellite Sound and Video Processor(衛(wèi)星探測和視頻處理器) |
| 中文描述： | 衛(wèi)星聲音和視頻處理器（衛(wèi)星探測和視頻處理器） |
| 文件頁數(shù)： | 18/27頁 |
| 文件大?。?/td> | 224K |
| 代理商： | STV0056AF |
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I
2
C PROTOCOL
1) WRITING
to the chip
S
-Start Condition
P
-Stop Condition
CHIPADDR
- 7 bits. Programmable06H or 46H(STV0056AFonly) with Pin HA.
W
-Write/Read bit is the 8th bit of the chip address.
A
-ACKNOWLEDGEafter receiving 8 bits of data/adress.
REGADDR
Address of register to be written to, 8 bits of which bits 3, 4, 5, 6 & 7 are ’X’ or
don’t care ie only the first 3 bitsare used
DATA
8 bitsofdatabeingwrittento theregister.All8 bitsmustbe writtento atthesame
time.
REGADDR/A/DATA/A
can be repeated,the write process can continue untill terminated with a STOP
condition. If the
REG ADDR
is higher than 07 then IIC PROTOCOL will still be
met (ie an
A
generated).
Example:
S
06
W
A
00
A
55
A
01
A
8F
A
P
2) READING
from the chip
Whenreading,thereis anauto-incrementfeature.Thismeansanyreadcommandalwaysstartsby reading
Reg 8 andwill continue to read the followingregisters in orderafter each acknowledge or untilthere is no
acknowledge or a stop. This function is cyclic that is it will read the same set of registers without
re-addressingthe chip. There are two modes of operationas set by writing to bit 7 of register 0. Read 3
registersin a cyclicfashionor all 5 registersin a cyclicfashion. Note only the last 5 of the11 registerscan
be read.
Reg0 bit 7 = L
Start/ chipadd / R /A/ Reg8 / A/ Reg9 / A/ Reg0A/ A/ Reg8 / A/ Reg9 / A/ Reg0A
/... / P /
Reg0 bit 7 = H
Start/ chipadd / R / A/ Reg 8 / A/ Reg9 / A/ Reg 0A/ A/ Reg7 / A/ Reg 6 / A / Reg8
/ A/ Reg9 / A/ Reg0A / A/ Reg 7 / A/ Reg 6 / ... / P /
CONTROL REGISTERS
Reg 0
Bit (default00
HEX
)
0
L
Select 5 bitsaudio volume control
1
L
Select 5 bitsaudio volume control
2
L
Select 5 bitsaudio volume control
3
L
Select 5 bitsaudio volume control
4
L
Select 5 bitsaudio volume control
5
L
Audio mux switch K4 - ANRSI/P select (L= PLL)
6
L
Audio mux switch K3 - ANRSselect (L = no ANRS, H = ANRS)
7
L
L = read 3 registers,H = read 5 registers
writeonly
00H = MUTE
01H = -26.75dB
: : : :
1.25dB steps up to
1FH = +12dB
:
Reg 1
Bit (default00
HEX
)
0
L
Select video gain bits
1
L
Select video gain bits
2
L
Select video gain bits
3
L
Select video gain bits
4
L
Select video gain bits
5
L
Select video gain bits
6
L
Selectedvideo invert (H = inverted, L= non inverted)
7
L
Videodeemphasis1 / Videodeemphasis2 (L: V
ID
De-em 1)
writeonly
00H = 0dB
01H = +0.202dB
02H = +0.404dB
n
= + 0.202 dB * n
3FH = + 12.73 dB
STV0056AF
18/27
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