參數(shù)資料
型號: STR910FM92X6T
廠商: 意法半導(dǎo)體
英文描述: ARM966E-S TM 16/32-Bit Flash MCU with Ethernet, USB, CAN, AC motor control, 4 timers, ADC, RTC, DMA
中文描述: ARM966E - ?商標16/32位閃存微控制器與以太網(wǎng),USB,加拿大,交流電機控制,4個定時器,模數(shù)轉(zhuǎn)換器,RTC和DMA的
文件頁數(shù): 13/73頁
文件大小: 595K
代理商: STR910FM92X6T
STR91xF
Functional overview
13/73
See
Table 2
for recommended interrupt source assignments to physical IRQ interrupt channels.
Interrupt source assignments are made by CPU firmware during initialization, thus establishing
interrupt priorities.
Table 2.
VIC IRQ Channel
Recommended IRQ Channel assignments (set by CPU firmware)
Logic Block
Interrupt Source
0 (high priority)
1
2
3
4
5
6
7
8
9
10
WatchDog
CPU Firmware
CPU Core
CPU Core
TIM Timer 0
TIM Timer 1
TIM Timer 2
TIM Timer 3
USB
USB
CCU
Timeout in WDT mode, Terminal Count in Counter Mode
Firmware generated interrupt
Debug Receive Command
Debug Transmit Command
Logic OR of ICI0_0, ICI0_1, OCI0_0, OCI0_1, Timer overflow
Logic OR of ICI1_0, ICI1_1, OCI1_0, OCI1_1, Timer overflow
Logic OR of ICI2_0, ICI2_1, OCI2_0, OCI2_1, Timer overflow
Logic OR of ICI3_0, ICI3_1, OCI3_0, OCI3_1, Timer overflow
Logic OR of high priority USB interrupts
Logic OR of low priority USB interrupts
Logic OR of all interrupts from Clock Control Unit
Logic OR of Ethernet MAC interrupts via its own dedicated
DMA channel.
Logic OR of interrupts from each of the 8 individual DMA
channels
Logic OR of all CAN interface interrupt sources
Logic OR of 8 Induction Motor Control Unit interrupts
End of AtoD conversion interrupt
Logic OR of 5 interrupts from UART channel 0
Logic OR of 5 interrupts from UART channel 1
Logic OR of 5 interrupts from UART channel 2
Logic OR of transmit, receive, and error interrupts of I2C
channel 0
Logic OR of transmit, receive, and error interrupts of I2C
channel 1
Logic OR of all interrupts from SSP channel 0
Logic OR of all interrupts from SSP channel 1
LVD warning interrupt
Logic OR of Alarm, Tamper, or Periodic Timer interrupts
Logic OR of all 32 inputs of Wake-Up unit (30 pins, RTC, and
USB Resume)
Logic OR of 8 interrupt sources: RTC, USB Resume, pins
P3.2 to P3.7
Logic OR of 8 interrupts from pins P5.0 to P5.7
Logic OR of 8 interrupts from pins P6.0 to P6.7
Logic OR of 8 interrupts from pins P7.0 to P7.7
USB Bus Resume Wake-up (also input to wake-up unit)
Special use of interrupts from Prefetch Queue and Branch
Cache
11
Ethernet MAC
12
DMA
13
14
15
16
17
18
CAN
IMC
ADC
UART0
UART1
UART2
19
I2C0
20
I2C1
21
22
23
24
SSP0
SSP1
BROWNOUT
RTC
25
Wake-Up (all)
26
Wake-up Group 0
27
28
29
30
Wake-up Group 1
Wake-up Group 2
Wake-up Group 3
USB
31 (low priority)
PFQ-BC
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