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參數(shù)資料
| 型號： | STR910FM92X6T |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | ARM966E-S TM 16/32-Bit Flash MCU with Ethernet, USB, CAN, AC motor control, 4 timers, ADC, RTC, DMA |
| 中文描述： | ARM966E - ?商標(biāo)16/32位閃存微控制器與以太網(wǎng)，USB，加拿大，交流電機(jī)控制，4個定時器，模數(shù)轉(zhuǎn)換器，RTC和DMA的 |
| 文件頁數(shù)： | 10/73頁 |
| 文件大?。?/td> | 595K |
| 代理商： | STR910FM92X6T |
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Functional overview
STR91xF
10/73
2.5
SRAM (64K or 96K Bytes)
A 32-bit wide SRAM resides on the CPU’s Data TCM (D-TCM) interface, providing single-cycle
data accesses. As shown in
Figure 1
, the D-TCM shares SRAM access with the Advanced
High-performance Bus (AHB). Sharing is controlled by simple arbitration logic to allow the DMA
unit on the AHB to also access to the SRAM.
2.5.1
Arbitration
Zero-wait state access occurs for either the D-TCM or the AHB when only one of the two is
requesting SRAM. When both request SRAM simultaneously, access is granted on an
interleaved basis so neither requestor is starved, granting one 32-bit word transfer to each
requestor before relinquishing SRAM to the other. When neither the D-TCM or the AHB are
requesting SRAM, the arbiter leaves access granted to the most recent user (if D-TCM was last
to use SRAM then the D-TCM will not have to arbitrate to get access next time).
The CPU may execute code from SRAM through the AHB. There are no wait states as long as
the D-TCM is not contending for SRAM access and the AHB is not sharing bandwidth with
peripheral traffic. The ARM966E-S CPU core has a small pre-fetch queue built into this
instruction path through the AHB to look ahead and fetch instructions during idle bus cycles.
2.5.2
Battery backup
When a battery is connected to the designated battery backup pin (VBATT), SRAM contents
are automatically preserved when the normal operating voltage on VDD pins is lost or sags
below threshold. Automatic switchover to SRAM can be disabled by firmware if it is desired that
the battery will power only the RTC and not the SRAM during standby.
2.6
DMA data movement
DMA channels on the Advanced High-performance Bus (AHB) take full advantage of the
separate data path provided by the Harvard architecture, moving data rapidly and largely
independent of the instruction path. There are two DMA units, one is dedicated to move data
between the Ethernet interface and SRAM, the other DMA unit has eight programmable
channels with 16 request signals to service other peripherals and interfaces (USB, SSP, I2C,
UART, Timers, EMI, and external request pins). Both single word and burst DMA transfers are
supported. Memory-to-memory transfers are supported in addition to memory-peripheral
transfers. DMA access to SRAM is shared with D-TCM accesses, and arbitration is described
in
Section 2.5.1
. Efficient DMA transfers are managed by firmware using linked list descriptor
tables. Of the 16 DMA request signals, two are assigned to external inputs. The DMA unit can
move data between external devices and resources inside the STR91xF through the EMI bus.
2.7
Non-volatile memories
There are two independent 32-bit wide Burst Flash memories enabling true read-while-write
operation. The Flash memories are single-voltage erase/program with 20 year minimum data
retention and 100K minimum erase cycles. The primary Flash memory is much larger than the
secondary Flash.
Both Flash memories are blank when devices are shipped from ST. The CPU can boot only
from Flash memory (configurable selection of which Flash bank).
相關(guān)PDF資料 |
PDF描述 |
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| STR910FM94X6T | ARM966E-S TM 16/32-Bit Flash MCU with Ethernet, USB, CAN, AC motor control, 4 timers, ADC, RTC, DMA |
| STR910FW32X6 | ARM966E-S TM 16/32-Bit Flash MCU with Ethernet, USB, CAN, AC motor control, 4 timers, ADC, RTC, DMA |
| STR910FW42X6T | ARM966E-S TM 16/32-Bit Flash MCU with Ethernet, USB, CAN, AC motor control, 4 timers, ADC, RTC, DMA |
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| STR910FW92X6T | ARM966E-S TM 16/32-Bit Flash MCU with Ethernet, USB, CAN, AC motor control, 4 timers, ADC, RTC, DMA |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| STR910FM94X6T | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:ARM966E-S TM 16/32-Bit Flash MCU with Ethernet, USB, CAN, AC motor control, 4 timers, ADC, RTC, DMA |
| STR910FW32X6 | 功能描述:ARM微控制器 - MCU TQFP 128 14x14x1.4 1 RoHS:否 制造商:STMicroelectronics 核心:ARM Cortex M4F 處理器系列:STM32F373xx 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:72 MHz 程序存儲器大小:256 KB 數(shù)據(jù) RAM 大小:32 KB 片上 ADC:Yes 工作電源電壓:1.65 V to 3.6 V, 2 V to 3.6 V, 2.2 V to 3.6 V 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:LQFP-48 安裝風(fēng)格:SMD/SMT |
| STR910FW32X6 | 制造商:STMicroelectronics 功能描述:256K Flash 64K sram CAN |
| STR910FW32X6T | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:ARM966E-S 16/32-Bit Flash MCU with Ethernet, USB, CAN, AC Motor Control, 4 Timers, ADC, RTC, DMA |
| STR910FW34X6T | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:ARM966E-S 16/32-Bit Flash MCU with Ethernet, USB, CAN, AC Motor Control, 4 Timers, ADC, RTC, DMA |
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