參數(shù)資料
型號(hào): STPCI2HEYI
廠商: STMICROELECTRONICS
元件分類: 外設(shè)及接口
英文描述: MULTIFUNCTION PERIPHERAL, PBGA516
封裝: PLASTIC, BGA-516
文件頁數(shù): 52/109頁
文件大?。?/td> 2430K
代理商: STPCI2HEYI
STPC ATLAS
Issue 1.1 - March 23, 2004
47/109
Note 1: PCI clock at 33MHz
4.5. AC CHARACTERISTICS
This section lists the AC characteristics of the
STPC interfaces including output delays, input
setup requirements, input hold requirements and
output float delays. These measurements are
based on the measurement points identified in
Figure 4-1 and Figure 4-2. The rising clock edge
reference level VREF and other reference levels
are shown in Table 4-9 below. Input or output
signals must cross these levels during testing.
Figure 4-1 shows output delay (A and B) and input
setup and hold times (C and D). Input setup and
hold times (C and D) are specified minimums,
defining the smallest acceptable sampling window
a synchronous input signal must be stable for
correct operation.
WLC
White Level Current
15.00 mA
18.50 mA
Table 4-4. RAMDAC DC Specification
Symbol
Parameter
Min
Max
Table 4-5. VGA RAMDAC Power Consumption
DCLK
(MHz)
DAC mode
(State)
PMax (mW)
VDD_DAC = 2.45V
VDD_DAC = 2.7V
-
Shutdown
0
6.25 - 135
Active
150
180
Table 4-6. 2.5V Power Consumptions (VCORE + VDD_x_PLL + VDD_DAC)
HCLK
(MHz)
CPUCLK
(MHz)
MCLK
(MHz)
Mode
DCLK
(MHz)
PMU
(State)
PMax (W)
V2.5V=2.45V
V2.5V=2.7V
66
133 (x2)
66
SYNC
Stopped
Stop Clock
1.5
1.9
Full Speed
2.5
3.0
135
Stop Clock
2.1
2.6
Full Speed
2.1
3.6
66
133 (x2)
90
ASYNC
Stopped
Stop Clock
1.9
2.4
Full Speed
2.8
3.5
135
Stop Clock
2.5
3.1
Full Speed
3.3
4.1
Table 4-7. 3.3V Power Consumptions (VDD)
HCLK
(MHz)
CPUCLK
(MHz)
MCLK
(MHz)
DCLK
(MHz)
PMU
(State)
PMax
(mW)
66
133 (x2)
66
6.26
Full Speed
130
135
215
66
133 (x2)
90
6.26
Full Speed
150
135
240
Table 4-8. PLL Power Consumptions
PLL name
PMax (mW)
VDD_PLL = 2.45V
VDD_PLL = 2.7V
VDD_DCLK_PLL
5
10
VDD_DEVCLK_PLL
5
10
VDD_HCLKI_PLL
5
10
VDD_HCLKO_PLL
5
10
VDD_MCLKI_PLL
5
10
VDD_MCLKO_PLL
5
10
VDD_PCICLK_PLL
5
10
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