參數(shù)資料
型號(hào): STPCD0112BTC3
元件分類: 32位微控制器
英文描述: 32-Bit Microprocessor
中文描述: 32位微處理器
文件頁數(shù): 43/61頁
文件大?。?/td> 1007K
代理商: STPCD0112BTC3
ELECTRICAL SPECIFICATIONS
Issue 2.2 - October 13, 2000
43/61
10e
4
11
4
SA[19:0] & SBHE valid before IOR#, IOW# asserted
XTALO to IOW# valid
11a
4
Memory access to 16 bit ISA Slave - 2BCLK
11b
4
Memory access to 16 bit ISA Slave - Standard 3BCLK
11c
4
Memory access to 16 bit ISA Slave - 4BCLK
11d
4
Memory access to 8 bit ISA Slave - 2BCLK
Memory access to 8 bit ISA Slave - Standard 3BCLK
ALE# asserted before ALE# negated
ALE# asserted before MEMR#, MEMW# asserted
13a
4
Memory Access to 16 bit ISA Slave
13b
4
Memory Access to 8 bit ISA Slave
ALE# asserted before SMEMR#, SMEMW# asserted
13c
4
Memory Access to 16 bit ISA Slave
13d
4
Memory Access to 8 bit ISA Slave
ALE# asserted before IOR#, IOW# asserted
ALE# asserted before AL[23:17]
14a
4
Non compressed
14b
4
Compressed
ALE# asserted before MEMR#, MEMW#, SMEMR#, SMEMW# negated
15a
4
Memory Access to 16 bit ISA Slave- 4 BCLK
15e
4
Memory Access to 8 bit ISA Slave- Standard Cycle
ALE# negated before LA[23:17] invalid (non compressed)
ALE# negated before LA[23:17] invalid (compressed)
MEMR#, MEMW# asserted before LA[23:17]
22a
4
Memory access to 16 bit ISA Slave.
22b
4
Memory access to 8 bit ISA Slave.
MEMR#, MEMW# asserted before MEMR#, MEMW# negated
23b
4
Memory access to 16 bit ISA Slave Standard cycle
23e
4
Memory access to 8 bit ISA Slave Standard cycle
SMEMR#, SMEMW# asserted before SMEMR#, SMEMW# negated
23h
4
Memory access to 16 bit ISA Slave Standard cycle
23l
4
Memory access to 16 bit ISA Slave Standard cycle
IOR#, IOW# asserted before IOR#, IOW# negated
23o
4
Memory access to 16 bit ISA Slave Standard cycle
23r
4
Memory access to 8 bit ISA Slave Standard cycle
MEMR#, MEMW# asserted before SA[19:0]
24b
4
Memory access to 16 bit ISA Slave Standard cycle
24d
4
Memory access to 8 bit ISA Slave - 3BLCK
24e
4
Memory access to 8 bit ISA Slave Standard cycle
24f
4
Memory access to 8 bit ISA Slave - 7BCLK
SMEMR#, SMEMW# asserted before SA[19:0]
24h Memory access to 16 bit ISA Slave Standard cycle
24i
4
Memory access to 16 bit ISA Slave - 4BCLK
24k
4
Memory access to 8 bit ISA Slave - 3BCLK
24l
4
Memory access to 8 bit ISA Slave Standard cycle
Note; The signal numbering refers to
Table 4-10
Note 4; These timings are extracted from simulations and are not garanteed by testing
2T
Cycles
2T
2T
2T
2T
2T
1T
Cycles
Cycles
Cycles
Cycles
Cycles
Cycles
11e
4
12
4
13
4
2T
2T
Cycles
Cycles
13
4
2T
2T
2T
Cycles
Cycles
Cycles
13e
4
14
4
15T
15T
Cycles
Cycles
15
4
11T
11T
14T
14T
Cycles
Cycles
Cycles
Cycles
18a
4
18a
4
22
4
13T
13T
Cycles
Cycles
23
4
9T
9T
Cycles
Cycles
23
4
9T
9T
Cycles
Cycles
23
4
9T
9T
Cycles
Cycles
24
4
10T
10T
10T
10T
Cycles
Cycles
Cycles
Cycles
24
4
10T
10T
10T
10T
Cycles
Cycles
Cycles
Cycles
Table 4-8. ISA Bus AC Timing
Name
Parameter
Min
Max
Units
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