參數(shù)資料
型號: STPC12GEYI
廠商: 意法半導(dǎo)體
英文描述: X86 Core PC Compatible System-on-Chip for Terminals
中文描述: x86內(nèi)核PC兼容系統(tǒng)上的終端芯片
文件頁數(shù): 98/111頁
文件大小: 1896K
代理商: STPC12GEYI
DESIGN GUIDELINES
98/111
Issue 1.0 - July 24, 2002
6.4.4. PCI INTERFACE
6.4.4.1. Introduction
In order to achieve a PCI interface which work at
clock
frequencies
up
consideration has to be given to the timing of the
interface with all the various electrical and
physical constraints taken into consideration.
to
33MHz,
careful
6.4.4.2. PCI Clocking Scheme
The PCI Clocking Scheme deserves a special
mention here. Basically the PCI clock (PCICLKO)
is generated on-chip from HCLK through a
programmable delay line and a clock divider. The
nominal frequency is 33MHz. This clock must be
looped to PCICLKI and goes to the internal South
Bridge through a deskewer. On the contrary, the
internal North Bridge is clocked by HCLK, putting
some additionnal constraints on T
0
and T
1
.
Figure 6-28. Clock Scheme
HCLK PLL
1/2
1/3
1/4
clock
delay
Strap Options
PCICLKO
T
1
PCICLKI
HCLK
AD[31:0]
South
Bridge
North
Bridge
Deskewer
MUX
T
0
T
2
STPC
MD[30:27]
MD[17,4]
MD[7:6]
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