參數(shù)資料
型號: STP4NA100
廠商: 意法半導體
英文描述: 32BIT W/ CACHE, MMU, FPU
中文描述: ? -快速通道增強型功率MOS器件
文件頁數(shù): 1/5頁
文件大小: 77K
代理商: STP4NA100
STP4NA100
N - CHANNEL ENHANCEMENT MODE
FAST POWER MOS TRANSISTOR
PRELIMINARY DATA
I
TYPICAL R
DS(on)
= 2.9
I
±
30V GATE TO SOURCE VOLTAGE RATING
I
100% AVALANCHE TESTED
I
REPETITIVE AVALANCHE DATA AT 100
o
C
I
LOW INTRINSIC CAPACITANCES
I
GATE CHARGE MINIMIZED
I
REDUCED THRESHOLD VOLTAGE SPREAD
DESCRIPTION
This series of POWER MOSFETS represents
the most advanced high voltage technology.
The optmized cell layout coupled with a new
proprietary edge termination concur to give
the device low RDS(on) and gate charge,
unequalled
ruggedness
switching performance.
and
superior
APPLICATIONS
I
HIGH CURRENT, HIGH SPEED SWITCHING
I
SWITCH MODE POWER SUPPLIES (SMPS)
I
DC-AC CONVERTERS FOR WELDING
EQUIPMENT AND UNINTERRUPTIBLE
POWER SUPPLIES AND MOTOR DRIVE
INTERNAL SCHEMATIC DIAGRAM
ABSOLUTE MAXIMUM RATINGS
Symbol
V
DS
V
DGR
V
GS
I
D
I
D
I
DM
(
)
P
tot
Parameter
Value
1000
1000
±
30
4.2
2.6
16.8
125
1
-65 to 150
150
Unit
V
V
V
A
A
A
W
W/
o
C
o
C
o
C
Drain-source Voltage (V
GS
= 0)
Drain- gate Voltage (R
GS
= 20 k
)
Gate-source Voltage
Drain Current (continuous) at T
c
= 25
o
C
Drain Current (continuous) at T
c
= 100
o
C
Drain Current (pulsed)
Total Dissipation at T
c
= 25
o
C
Derating Factor
Storage Temperature
Max. Operating Junction Temperature
(
) Pulse width limited by safe operating area
T
stg
T
j
TYPE
V
DSS
1000 V
R
DS(on)
<3. 5
I
D
STP4NA100
4.2 A
October 1997
1
2
3
TO-220
1/5
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