參數(shù)資料
      型號(hào): STM708TM6F
      廠商: 意法半導(dǎo)體
      英文描述: 3V Supervisor
      中文描述: 3V的監(jiān)
      文件頁(yè)數(shù): 9/26頁(yè)
      文件大小: 251K
      代理商: STM708TM6F
      9/26
      STM706T/S/R; STM706P; STM708T/S/R
      OPERATION
      Reset Output
      The STM70x Supervisor asserts a reset signal to
      the MCU whenever V
      CC
      goes below the reset
      threshold (V
      RST
      ), a watchdog time-out occurs (if
      WDO is connected to MR), or when the Push-but-
      ton Reset Input (MR) is taken low. RST is guaran-
      teed to be a logic low (logic high for STM706P and
      STM708T/S/R) for V
      CC
      < V
      RST
      down to V
      CC
      =1V
      for T
      A
      = 0°C to 85°C.
      During power-up, once V
      CC
      exceeds the reset
      threshold an internal timer keeps RST low for the
      reset time-out period, t
      rec
      . After this interval RST
      returns high.
      If V
      CC
      drops below the reset threshold, RST goes
      low. Each time RST is asserted, it stays low for at
      least the reset time-out period (t
      rec
      ). Any time V
      CC
      goes below the reset threshold the internal timer
      clears. The reset timer starts when V
      CC
      returns
      above the reset threshold.
      Push-button Reset Input
      A logic low on MR asserts reset. Reset remains
      asserted while MR is low, and for t
      rec
      (see
      Figure
      29., page 19
      ) after it returns high. The MR input
      has an internal 40k
      pull-up resistor, allowing it to
      be left open if not used. This input can be driven
      with TTL/CMOS-logic levels or with open-drain/
      collector outputs. Connect a normally open mo-
      mentary switch from MR to GND to create a man-
      ual reset function; external debounce circuitry is
      not required. If MR is driven from long cables or
      the device is used in a noisy environment, connect
      a 0.1μF capacitor from MR to GND to provide ad-
      ditional noise immunity. MR may float, or be tied to
      V
      CC
      when not used.
      Watchdog Input (STM706T/S/R and STM706P)
      The watchdog timer can be used to detect an out-
      of-control MCU. If the MCU does not toggle the
      Watchdog Input (WDI) within t
      WD
      (1.6sec), the
      Watchdog Output pin (WDO) is asserted. The in-
      ternal 1.6sec timer is cleared by either:
      1.
      a reset pulse, or
      2.
      by toggling WDI (high-to-low or low-to-high),
      which can detect pulses as short as 50ns.
      See
      Figure 30., page 19
      for STM706T/S/R and
      STM706P.
      The timer remains cleared and does not count for
      as long as reset is asserted. As soon as reset is re-
      leased, the timer starts counting.
      Watchdog Output (STM706T/S/R and
      STM706P)
      When V
      CC
      drops below the reset threshold, WDO
      will go low even if the watchdog timer has not yet
      timed out. However, unlike the reset output, WDO
      goes high as soon as V
      CC
      exceeds the reset
      threshold. WDO may be used to generate a reset
      pulse by connecting it to the MR input.
      Power-fail Input/Output
      The Power-fail Input (PFI) is compared to an inter-
      nal reference voltage (independent from the V
      RST
      comparator). If PFI is less than the power-fail
      threshold (V
      PFI
      ), the Power-Fail Output (PFO) will
      go low. This function is intended for use as an un-
      dervoltage detector to signal a failing power sup-
      ply. Typically PFI is connected through an external
      voltage divider (see
      Figure 10., page 8
      ) to either
      the unregulated DC input (if it is available) or the
      regulated output of the V
      CC
      regulator. The voltage
      divider can be set up such that the voltage at PFI
      falls below V
      PFI
      several milliseconds before the
      regulated V
      CC
      input to the STM70x or the micro-
      processor drops below the minimum operating
      voltage.
      If the comparator is unused, PFI should be con-
      nected to V
      SS
      and PFO left unconnected. PFO
      may be connected to MR on the STM70x so that a
      low voltage on PFI will generate a reset output.
      Ensuring a Valid Reset Output Down to
      V
      CC
      = 0V
      When V
      CC
      falls below 1V, the state of the RST out-
      put can no longer be guaranteed, and becomes
      essentially an open circuit. If a high value pull-
      down resistor is added to the RST pin, the output
      will be held low during this condition. A resistor val-
      ue of approximately 100k
      will be large enough to
      not load the output under operating conditions, but
      still sufficient to pull RST to ground during this low
      voltage condition (see Figure
      11
      ).
      Figure 11. Reset Output Valid to Ground
      Circuit
      AI08844
      STM70x
      RST
      R1
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