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參數(shù)資料
| 型號： | STM32F103R8T7TR |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, FLASH, 1.25 MHz, RISC MICROCONTROLLER, PQFP64 |
| 封裝： | 10 X 10 MM, ROHS COMPLIANT, QFP-64 |
| 文件頁數(shù)： | 24/92頁 |
| 文件大?。?/td> | 1212K |
| 代理商： | STM32F103R8T7TR |
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Pinouts and pin description
STM32F103x8, STM32F103xB
Doc ID 13587 Rev 11
D4
-
97
-
PE0
I/O FT
PE0
TIM4_ETR
C4
-
98
-
PE1
I/O FT
PE1
E5
47
D4
63
99
36
VSS_3
SVSS_3
F5
48
E4
64
100
1
VDD_3
SVDD_3
1.
I = input, O = output, S = supply.
2.
FT = 5 V tolerant.
3.
Function availability depends on the chosen device. For devices having reduced peripheral counts, it is always the lower
number of peripheral that is included. For example, if a device has only one SPI and two USARTs, they will be called SPI1
and USART1 & USART2, respectively. Refer to Table 2 on page 10.
4.
If several peripherals share the same I/O pin, to avoid conflict between these alternate functions only one peripheral should
be enabled at a time through the peripheral clock enable bit (in the corresponding RCC peripheral clock enable register).
5.
PC13, PC14 and PC15 are supplied through the power switch. Since the switch only sinks a limited amount of current
(3 mA), the use of GPIOs PC13 to PC15 in output mode is limited: the speed should not exceed 2 MHz with a maximum
load of 30 pF and these IOs must not be used as a current source (e.g. to drive an LED).
6.
Main function after the first backup domain power-up. Later on, it depends on the contents of the Backup registers even
after reset (because these registers are not reset by the main reset). For details on how to manage these IOs, refer to the
Battery backup domain and BKP register description sections in the STM32F10xxx reference manual, available from the
STMicroelectronics website: www.st.com.
7.
Unlike in the LQFP64 package, there is no PC3 in the TFBGA64 package. The VREF+ functionality is provided instead.
8.
This alternate function can be remapped by software to some other port pins (if available on the used package). For more
details, refer to the Alternate function I/O and debug configuration section in the STM32F10xxx reference manual, available
from the STMicroelectronics website: www.st.com.
9.
The pins number 2 and 3 in the VFQFPN36 package, 5 and 6 in the LQFP48 and LQFP64 packages, and C1 and C2 in the
TFBGA64 package are configured as OSC_IN/OSC_OUT after reset, however the functionality of PD0 and PD1 can be
remapped by software on these pins. For the LQFP100 package, PD0 and PD1 are available by default, so there is no
need for remapping. For more details, refer to the Alternate function I/O and debug configuration section in the
STM32F10xxx reference manual.
The use of PD0 and PD1 in output mode is limited as they can only be used at 50 MHz in output mode.
Table 5.
Medium-density STM32F103xx pin definitions (continued)
Pins
Pin name
Ty
p
e
(1)
I/
O
L
e
vel
(2
)
Main
function(3)
(after reset)
Alternate functions(4)
LFBGA10
0
LQ
FP48
TFBGA64
LQ
FP64
LQ
FP100
VFQFP
N
36
Default
Remap
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| STM32F103R8T7XXX | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Medium-density performance line ARM-based 32-bit MCU with 64 or 128 KB Flash, USB, CAN, 7 timers, 2 ADCs, 9 communication interfaces |
| STM32F103R8U6TR | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Medium-density performance line ARM-based 32-bit MCU with 64 or 128 KB Flash, USB, CAN, 7 timers, 2 ADCs, 9 communication interfaces |
| STM32F103R8U6XXX | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Medium-density performance line ARM-based 32-bit MCU with 64 or 128 KB Flash, USB, CAN, 7 timers, 2 ADCs, 9 communication interfaces |
| STM32F103R8U7TR | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Medium-density performance line ARM-based 32-bit MCU with 64 or 128 KB Flash, USB, CAN, 7 timers, 2 ADCs, 9 communication interfaces |
| STM32F103R8U7XXX | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Medium-density performance line ARM-based 32-bit MCU with 64 or 128 KB Flash, USB, CAN, 7 timers, 2 ADCs, 9 communication interfaces |
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